Patent 5030946

Patent for VRAM access via VDC/CPU

Note: all mentions of "dot" have been replaced with "pixel"
Note: terminals with a High value are a binary 1 and Low is a binary 0.

Full Patent

Original Patent

United States Patent Number: 5030946
APPARATUS FOR THE CONTROL OF AN ACCESS TO A VIDEO MEMORY


Abstract



An apparatus for the control of an access to a video memory comprises a memory width register having a content of a number of pixel periods by which an access timing is determined to address a video memory. Therefore, an access timing is easily controlled dependent on a memory speed of the video memory only by changing the content of the memory width register. When the video memory is accessed during a display cycle of the video memory, video data may be stored in a buffer memory, and transferred from the buffer memory after the display cycle is finished.



Field of the Invention



The invention relates to an apparatus for the control of an access to a video memory, and more particularly to an apparatus for the control of an access to a video memory in which a number of pixel periods is controlled at the time of an access to a video memory and/or a timing of a data transfer is controlled during a display cycle of a video memory.



Background of the Invention



There has been used an apparatus for the control of an access to a video memory in which an access is allocated from a CPU to a video memory during the first half of 4 bits in a horizontal one character cycle of 8 bits, and an access is allocated to a character generator of the video memory during the latter half of 4 bits therein. In the apparatus for the control of an access to a video memory, flickers are prevented from being occurred on a screen because the writing and reading of data which are performed from the CPU to the video memory and the access to the character generator of the video memory are divided sequentially.
According to the apparatus for the control of an access to a video memory, however, there is a disadvantage that an access of the video memory can not be controlled in its timing because the access timing is fixed as mentioned before. In a personal computer in which a processing time is widely varied, for instance, from 40 ns to 139 ns dependent on a resolution of the screen, therefore, a property of the video memory is not sufficiently utilized even if the video memory is a high speed memory. On the other hand, a low speed memory can not be used in an apparatus in which a high speed memory is not required in view of a specified characteristic in a case where an access timing is fixed in a high speed mode.
There is a further disadvantage that a throughput of the CPU is decreased because the CPU has to wait the writing of data into the video memory and reading of data therefrom during a display cycle of the video memory, although flickers are prevented from being occurred on the screen.



Summary of the Invention



Accordingly, it is an object of the invention to provide an apparatus for the control of an access to a video memory in which an access to a video memory can be easily controlled in its timing dependent on a speed of a video memory.
It is another object of the invention to provide an apparatus for the control of an access to a video memory in which a throughput of a CPU is improved.
According to the invention, an apparatus for the control of an access to a video memory comprises:

register means storing a number of pixel signals for the access to a video memory
means for deciding said number of pixel periods in accordance with said content of said register means
means for addressing said video memory at timings determined in accordance with said number of pixel periods
means for latching video data which are read from said video memory at said timings
wherein a pattern defined by said video data is displayed on a screen.



Description of Preferred Embodiments




In [Figure 1], there is shown an apparatus for displaying an image on a screen which is mainly composed of a Video Display Controller (1), a CPU (2), a Video Color Encoder (3), and a Programmable Sound Generator (4). The Video Display Controller (1) supplies the Video Color Encoder (3) with image data for a story which are read from a VRAM (7) under the control of the CPU (2) reading a program stored in a ROM (5). The CPU (2) controls a RAM (6) to store data, calculation or arithmetical results etc. temporarily in accordance with a program stored in the ROM (5). The Video Color Encoder (3) is supplied with image data to produce RGB analog signals or video color signals including luminance signals and color difference signals to which the RGB signals are matrix-converted by using color data stored therein. The programmable sound generator 4 is controlled by the CPU (2) reading a program stored in the ROM (5) to produce audio signals making left and right stereo sounds. The video color signals produced at the Video Color Encoder (3) are of composite signals supplied through an interface (8) to a video display (9), while the RGB analog signals are directly supplied to a video display (9) which is used as an exclusive monitor apparatus. The left and right analog signals supplied from the Programmable Sound Generator (4) are amplified at amplifiers 11a and 11b to make sounds at speakers 12a and 12b.


 
  
[Figure 1] is a block diagram showing an apparatus for displaying an image on a screen in which an apparatus for the control of an access to a video memory according to the invention is included.



In [Figure 2A], there is shown the Video Display Controller (1) transferring data between the CPU (2) and VRAM (7) which comprises a control unit (20) including various kinds of registers to be described later, an address unit (21), a CPU read/write buffer (22), and sprite shift register (24), a background shift register (25), a data bus buffer (26), a synchronic circuit (27), and a priority circuit (28).
The control unit (20) is provided with a BUSY terminal being Low to keep the CPU (2) writing data into the VRAM (7) or reading data therefrom in a case where the Video Display Controller (1) is not in time for the writing or reading of the date, an IRQ terminal supplying an interruption request signal, a CK terminal receiving a clock signal of a frequency for one pixel periods (one picture element), a RESET terminal receiving a reset signal for initializing the Video Display Controller (1), and an EX 8/16 terminal receiving a data bus width signal for selecting one of 8 and 16 bit data buses.
The address unit (21) is connected to terminals MAO to MA15 supplying address signals for the VRAM (7) which has, for instance, a special address region of 65,536 words. The address unit (21), CPU read/write buffer (22), Sprite Attribute Table (23), sprite shift register (24), and background shift register (25) are connected to terminals MD 0 to MD 15 through which data are transferred to and from the VRAM (7).
The Sprite Attribute Table buffer (23) is a memory for storing X and Y display positions, pattern codes and control data of sprites each composed of 16×16 pixels as described in more detail later.
The sprite shift register (24) stores pattern and color data of a sprite read from a sprite generator in the VRAM (7) which is accessed in accordance with the pattern codes stored in the Sprite Attribute Table (23) as described in more detail later.
The background shift register (25) stores pattern data, along with CG color, read from a character generator in the VRAM (7) in accordance with an address based on a character code of a background attribute table in the VRAM (7) which is accessed in an address decided by a raster position as also described in more detail later.
The data bus buffer (26) is connected to terminals D0 to D15 through which data are supplied and received. In the Video Display Controller (1), 8 or 16 bit interface is selected to comply with a data width of a system including the CPU2 wherein the terminals D0 to D7 among the terminals D0 to D15 are occupied when the 8 bit interface is selected.
The synchronic circuit (27) is connected to a DISP terminal indicating a display period, a VSYNC terminal from which a vertical synchronous signal for a video display (9) is supplied and in which an external vertical synchronous signal is received, and a HSYNC terminal from which a horizontal synchronous signal for a video display (9) is supplied and in which an external horizontal synchronous signal is received.
The priority circuit (28) is connected to terminals VD0 to VD7 through which video signals are supplied, and a SP/BG (VD8) terminal being High when the video signals are of a sprite and being Low when the video signals are of a background.
The aforementioned control unit (20) is also connected to a CS terminal being Low wherein the CPU (2) is able to read data from registers therein and sprite data thereinto, a RD terminal receiving a clock signal for the reading thereof, a WR terminal receiving a clock signal for the writing thereof, and terminals A0 and A1 which are connected to address bus of the CPU (2). Further, the Video Display Controller (1) is provided with a MRD terminal being Low when the CPU (2) reads data from the VRAM (7), and a MWR terminal being Low when the CPU (2) writes data into the VRAM (7).


 
  
[Figure 2] is a block diagram showing a video display controller for the control of writing video signals into a VRAM and reading video signals therefrom.



In [Figure 2B], there is shown an apparatus for displaying a sprite on a screen which is included in the apparatus of [Figure 1] wherein the reference numerals 31 and 32 indicate a sprite attribute table and sprite generator in the VRAM (7) respectively. The Sprite Attribute Table (31) can include, for instance, sixty-four sprites, while the Sprite Generator (32) can include, for instance, one thousand and twenty-four sprites. In the Sprite Attribute Table (31), addresses of 0 to 63 are assigned to the sixty-four sprites to give a priority thereto in the order of the address 0>1>. . . >62>63. Each of the sprites is composed of 16×16 bits, and includes X and Y coordinates, pattern codes and control data. As to each of the sprites, the Y coordinate is compared with a raster signal supplied from a scanning raster producing circuit 33 in a coincidence detection circuit (34) whereby sprites each having a Y coordinate coincident with a raster signal are stored into a pattern code buffer (35) which can store a maximum number of 16 sprites by referring to a corresponding one of the addresses 0 to 63. A selector (36) selects a pattern code of the Sprite Attribute Table (31) in accordance with an address stored in the pattern code buffer (35) to access the Sprite Generator (32) in regard to an address which is of a selected pattern code, thereby reading pattern data from the Sprite Generator (32). The pattern data thus obtained are stored into a pattern data buffer (37) along with an X coordinate corresponding thereto read from the Sprite Attribute Table (31). The storing of sprites into the pattern code buffer (35) is performed at a horizontal display period preceding to the present horizontal display period by one scanning raster, while the storing of pattern data into the pattern data buffer (37) is performed at a following horizontal retrace period. When a scanning raster at which pattern data are displayed has come, the X coordinate thus stored in the pattern data buffer (37) is compared with a counted value of a horizontal pixel period clock counter 38 in a coincidence detection circuit (39) whereby pattern data having an X coordinate coincident with the counted value are supplied to a parallel/serial converting circuit (40). In the parallel/serial converting circuit (40), parallel pattern data are converted into serial pattern data which are supplied through a gate circuit (42) to a video display (9). The gate circuit (42) is controlled to be turned on and off in accordance with a content of a starting coordinates registration circuit (43) by the CPU (2). The content thereof is X and Y coordinates by which the starting coordinates of a display region is defined on a display screen.


 
  
[Figure 2] is a block diagram showing an apparatus for displaying a sprite on a screen in the apparatus of [Figure 1].


 

In [Figures 3A to 3U], there are shown various kinds of registers included in the Control Unit (20)
           of the Video Display Controller (1).

   (a) Address Register ([Figure 3A])
          A register number AR is exclusive written into the address register designating one of
          the memory address write register to DMA VRAM-SATB source address register as shown in
          [Figures 3C to 3U] so that data are writing into the Video Display Controller (1) under the
          condition that the A1 and CS terminals thereof are Low.

          In a case where 16 bit data bus is selected, the EX 8/16 terminal is 0, the A1
          terminal is 0, the R/W terminal is W, and the A0 terminal is no matter.

          In a case where 8 bit data bus is selected, the EX 8/16 terminal is 1, the A0
          and A1 terminals are 0, and the R/W terminal is W.


 
  
[Figure 3A] Address Register (AR)


 
   (b) Status Register ([Figure 3B])
          A bit corresponding to one of interruption jobs is set to be High in the status register
          to make the interruption active when a cause of the interruption which is enabled by an
          interruption permission bit of a Control Register and DMA Control Register as showing in
          [Figures 3G and 3Q] is occurred.  When the status is read from the status register, the
          corresponding bit is cleared automatically.

          The status indicating bits are as follows.

          (1) bit 0 (CR) - collision of sprites
              It is indicated that the sprite number 0 of a sprite is collided with any one of the
              sprite numbers 1 to 63 of sprites.

          (2) bit 1 (OR) - more sprites than a predetermined number
              (2.1) a case where more than 17 sprites are detected on a single raster line.
              (2.2) a case where data of a sprites which is designated are not transferred to a
                    data buffer in a horizontal trance period.
              (2.3) a case where a bit of CGX in control data of a sprite by which two sprites are
                    joined in a horizontal direction is set so that data of the sprites are not
                    transferred to a data buffer.

          (3) bit 2 (PR) - detection of raster
              It is indicated that a value of a raster counter becomes a predetermined value of a
              raster detecting register.

          (4) bit 4 (DS) - finishing of DMA transfer
              It is indicated that data transfer between the VRAM (7) and Sprite Attribute Table
              buffer (23) is finished.

          (5) bit 4 (DV) - finishing of DMA transfer
              It is indicated between two regions of VRAM (7) is finished.

          (6) bit 5 (VD) - vertical retrace period
              It is indicated that the VRAM (7) accessed for the writing or reading of data by the
              CPU (2) so that the BUSY terminals is 0.


 
  
[Figure 3B] Status Register (SR)


 
   (c) Memory Address Write Register (register name 0x00, [Figure 3C])
          A starting address MAWR is written into the memory address write register so that the
          writing of data begins at the starting address of the VRAM (7).


 
  
[Figure 3C] Memory Address Write Register (MAWR)


 
   (d) Memory Address Read Register (register number 0x01, [Figure 3D])
          A starting address MARR is written into the memory address read register.  When the
          upper byte of the starting address is written thereinto, data are begun to be read from
          the starting address of the VRAM (7) so that data thus read are written into a VRAM data
          read register as showing in [Figure 3F].  There after, the starting address MARR is
          automatically incremented by one.


 
  
[Figure 3D] Memory Address Read Register (MARR)


 
   (e) VRAM Data Write Register (register number 0x02, [Figure 3E])
          Data which are transferred from the CPU (2) to the VRAM (7) are written into the VRAM data
          write register.  When the upper byte of the data VWR is written thereinto, the Video
          Display Controller (1) begins to write the data into the VRAM (7) and the address MAWR of
          the memory address write register is automatically incremented by one upon writing of the
          data.


 
  
[Figure 3E] VRAM Data Write Register (VWR)


 
   (f) VRAM Data Read Register (register number 0x02, [Figure 3F])
          Data which are transferred from the VRAM (7) to the CPU (2) are written into the VRAM data
          read register.  When the upper byte of the data VRR is read therefrom, the reading of
          data is performed at the following address of the VRAM (7).


 
  
[Figure 3F] VRAM Data Read Register (VRR)


 
   (g) Control Register (register number 0x05, [Figure 3G])
          An operating mode of the Video Display Controller (1) is controlled in accordance with the
          following bits of the Control Register.

          (1) bits 0 to 3 (IE) - enable of interruption request
              (1.1) bit 0 - collision detection of sprites
              (1.2) bit 1 - excess number detection of sprites
              (1.3) bit 2 - raster detection
              (1.4) bit 3 - detection of vertical retrace period

          (2) bits 4 and 5 (EX) - external synchronization

        

          (3) bit 6 (SB) - sprite blanking
              It is decided whether a sprite should be displayed on a screen or not.
              The control of the bit is effective in the following Horizontal Display Period.
              (3.1) 0 - blanking of a sprite
              (3.2) 1 - display of a sprite

          (4) bit 7 (BB) - background blanking
              It is decided whether background should be displayed on a screen or not.
              The control of the bit is effective in the following Horizontal Display Period.
              (4.1) 0 - blanking of background
              (4.2) 1 - display of background.

          (3.4) As a result, when bits 6 and 7 are both 0, there is a resulted "burst mode" in
              which the following operations can be performed.
              (3.4.1) The access to the VRAM (7) is not performed for a display, but the VRAM (7) is
                      accessed by the CPU (2).
              (3.4.2) DMA between two regions of the VRAM (7) is possible to be performed at any
                      time.

              In such occasions, the terminals VD0 and VD7 are all Low while the SP/BG terminal is
              High. On the other hand, when the bits 6 and 7 are both 1, there is released from
              the "burst mode".

          (5) bits 8 and 9 (TE) - selection of DISP terminal outputs

        

          (6) bit 10 (DR) - dynamic RAM refresh
              Refresh address is supplied from the terminals MA0 to MA15 upon the setting of the
              bit in a case where VRAM pixel width is of 2 pixels or 4 pixels for background in a memory
              width register as showing in [Figure 3K].

          (7) bits 11 and 12 (IW) - increment width selection of memory address write register or
              memory address read register
              A width which is incremented in address is selected as follows.

        

              In a case of 8 bit access, an address is incremented upon the upper byte.



 
  
[Figure 3G] Control Register (CR)


 
   (h) Raster Detecting Register (register number 0x06, [Figure 3H])
          A raster number RCR at which an interruption job is performed is written into the
          raster detecting register.  An interruption signal is produced when a value of a raster
          counter is equal to the raster number RCR.  The raster counter is preset to be 64 at
          a preceding scanning raster line to a display starting raster line as described in more
          detail later, and is increased at each raster line by one.


 
  
[Figure 3H] Raster Detecting Register (RDR)


 
   (i) BGX Scroll Register (register number 0x07, [Figure 3I])
          The BGX scroll register is used for a horizontal scroll of background on a screen.  When
          a content BXR is rewritten therein, the content is effective in the following raster
          line.


 
  
[Figure 3I] BGX Scroll Register (BGX)


 
   (j) BGY Scroll Register (register number 0x08, [Figure 3J])
          The BGY scroll register is used for a vertical scroll of background on a screen.  When a
          content BYR is rewritten therein, the content is effective to be as "BYR + 1" in the
          following raster line.


 
  
[Figure 3J] BGY Scroll Register (BGY)


 
   (k) Memory Width Register (register number 0x09, [Figure 3K])
          (1) bits 0 and 1 (VM) - VRAM pixel width
              A pixel width in which an access to the Background Attribute Table and character
              generator, DMA and access of the CPU (2) to the VRAM (7) during a horizontal display
              period are performed is written into the bits of the memory width register.  The pixel
              width is decided dependent on a memory speed of the VRAM (7).  When the bits 0 and 1
              are re-written therein, the content is effective at the beginning of a vertical
              retrace period.
        
              BAT is for Background Attribute Table, and CG is for character generator.

          (2) bits 2 and 3 (SM) - sprite pixel width
              A pixel width which an access to the sprite generator is performed during a horizontal
              retrace period is written into the bits of the memory width register.
        
          (3) bits 4 to 6 (SCREEN)
              The number of character in X and Y directions of a fictitious screen is decided
              dependent on the content of the bits.  When a content is effective at the beginning
              of a vertical retrace period.

        

          (4) bit 4 (CM) - CG mode
              When a VRAM pixel width is of 4 pixels, a color block of a character generator is
              changed dependent on the bit. A content is writtent into the bit, the content is
              effective in the following raster line.



 
  
[Figure 3K] Memory Width Register (MWR - not to be confused with terminal MWR)


 
   (l) Horizontal Synchronous Register (register number 0x0A, [Figure 3L])
          (1) bits 1 to 4 (HSW) - horizontal synchronous pulse
              A pulse width of Low level of a horizontal synchronous pulse is set as an unit of a
              character cycle. One of 1 to 32 is selected by using 5 bits to comply with the
              specification of a video display.

          (2) bits 8 to 14 (HDS) - starting position of horizontal display
              A period between a rising edge of a character cycle.  An optimum position in a
              horizontal direction on a video display is decided by a content of the 7 bits.  When
              it is assumed that a horizontal display position (horizontal back porch) is N,
              N - 1 is written into HDS bits.


 
  
[Figure 3L] Horizontal Synchronous Register (HSR)


 
   (m) Horizontal Display Register (register number 0x0B, [Figure 3M])
          (1) bits 0 to 6 (HDW) - horizontal display width
              A display period in each raster line is set as an unit of a character cycle, and is
              decided in accordance with the number of characters in the horizontal direction on a
              video display dependent on a content of the 7 bits.  If it is assumed that a horizontal
              display position is N, N - 1 is written into HDW bits.

          (2) bits 8 to 11 (HDE) - horizontal display ending position
              A period between an ending of a Horizontal Display Period and a rising edge of a
              horizontal synchronous signal is set as an unit of a character cycle.  An optimum
              position of a horizontal display is set on a video display by the 7 bits.  When it is
              assumed that a horizontal display ending position (horizontal back porch) is N,
              N -1 is written into HDE bits.


 
  
[Figure 3M] Horizontal Display Register (HDR)


 
   (n) Vertical Synchronous Register (register number 0x0C, [Figure 3N])
          (1) bits 0 to 4 (VSW) - vertical synchronous pulse width
              A pulse width of a vertical synchronous signal is decided in a width of Low level
              as a unit of a raster line.  One of 1 to 32 is selected to comply with a
              specification of a video display.

          (2) bits 8 to 15 (VDS) - vertical display starting position
              A period between a rising edge of a vertical synchronous signal and a vertical
              synchronous starting position is set as an unit of a raster line.  When it is assumed
              that a vertical display starting position (vertical back porch) is N, N-2 is
              written into the bits.


 
  
[Figure 3N] Vertical Synchronous Register (VSR)


 
   (o) Vertical Display Register (register number 0x0D, [Figure 3O])
          A vertical display period (display region) is set as an unit of a raster line.  A
          vertical display width is decided in accordance with the number of raster lines to be
          displayed on a video display which is defined by a content of the 9 bits.  When it is
          assumed that a vertical display width is N, N - 1 is written into the VDW bits.


 
  
[Figure 3O] Vertical Display Register / Vertical Display Width (VDW)


 
   (p) Vertical Display Ending Position Register (register number 0x0E, [Figure 3P])
          A period between a vertical display ending position and a rising edge of a vertical
          synchronous signal is set as an unit of a raster line.  When it is assumed that a
          vertical optimum position (vertical front porch) is N to be defined by the 8 bits,
          N is written into the VCR bits.


 
  
[Figure 3P] Vertical Display Ending Position Register / Vertical C..... R..... (VCR)


 
   (q) DMA Control Register (register number 0x0F, [Figure 3Q])
          (1) bit 0 (DSC) - Enable an interruption at the finishing of transfer between the
              VRAM (7) and Sprite Attribute Table buffer (23).
              It is decided whether or not an interruption is enabled at the finishing time of
              the transfer.
              (1.1) 0 - disable
              (1.2) 1 - enabled

          (2) bit 1 (DVC) - Enable an interruption at the finishing of transfer between two
              regions of the VRAM (7).
              It is decided whether or not an interruption is enabled finishing time of the
              transfer.
              (2.1) 0 - disable
              (2.2) 1 - enabled

          (3) bit 2 (SI/D) - Increment/decrement of a source address
              One of automatically increment and decrement of a source address is selected in a
              transfer between two regions of VRAM (7).
              (3.1) 0 - increment
              (3.2) 1 - decrement

          (4) bit 3 (DI/D) - Increment/decrement of a destination address
              One of automatically increment and decrement of a destination address is selected in a
              transfer between two regions of VRAM (7).
              (4.1) 0 - increment
              (4.2) 1 - decrement

          (5) bit 4 (DSR) - repetition of a transfer between the VRAM (7) and the Sprite
              Attribute Table buffer (23) is enabled.
              (5.1) 0 - disable
              (5.2) 1 - enabled


 
  
[Figure 3Q] DMA Control Register (DCR)


 
   (r) DMA Source Address Register (register number 0x10, [Figure 3R])
          A starting address of a source address is allocated in a transfer between two regions
          of the VRAM (7).


 
  
[Figure 3R] DMA Source Address Register (SOUR)


 
   (s) DMA Destination Address Register (register number 0x11, [Figure 3S])
          A starting address of a destination address is allocated in a transfer between two
          regions of the VRAM (7).


 
  
[Figure 3S] DMA Destination Address Register (DESR)


 
   (t) DMA Block Length Register (register number 0x12, [Figure 3T])
          A length of a block is defined in a transfer between two regions of the VRAM (7).


 
  
[Figure 3T] DMA Block Length Register (LENR)


 
   (u) DMA VRAM-SATB Source Address Register (register number 0x13, [Figure 3U])
          A starting address of a source address is allocated in a transfer between the VRAM (7)
          and Sprite Attribute Table buffer (23).


 
  
[Figure 3U] DMA VRAM-SAT Source Address Register (DVSSR)



In [Figure 4A, there is shown an address in a background attribute table for a character on a fictitious screen. A character and color to be displayed at each character position are stored in the background attribute table. A predetermined number of background attribute tables are stored in a region the first address of which is 0 in the VRAM (7). The fictitious screen shown therein which is one example is of 32×32 characters (1F=32).


 
  
[Figure 4A] is an explanatory diagram showing a fictitious screen in the apparatus of [Figure 1].



In [Figure 4B, there is shown a screen which is framed by writing respective predetermined values into the aforementioned horizontal synchronous register, horizontal display register, vertical synchronous register and vertical display register as shown in [Figures 3L, 3M, 3N and 3O]. Although the respective predetermined values for the registers are not explained here, a display region is defined in accordance with "HDW+1" in the horizontal display register and "VDW+1" in the vertical display register. In the embodiment, the starting coordinates (x,y) for the display region is indicated to be as (32, 64).


 
  
[Figure 4B] is an explanatory diagram showing a display region on a screen in the apparatus of [Figure 1].



In [Figures 5A and 5B], there are shown background attribute tables (BATs) in the VRAM (7) each of 16 bits to have a character code of lower 12 bits for designating a pattern number of a character and a CG color of upper 4 bits for designating a CG color code.


 
  
[Figure 5A and 5B] are explanatory diagrams showing a background attribute table in the VRAM in the apparatus of [Figure 1].



[Figures 6A and 6B]


 
  
[Figures 6A and 6B] are explanatory diagrams showing a sprite attribute table in the VRAM in the apparatus of [Figure 1].



[Figure 7]


 
  
[Figure 7] is an explanatory diagram explaining an operation in which a sprite is moved on a screen in the apparatus of [Figure 1].



[Figure 8]


 
  
[Figure 8] is an explanatory diagram explaining an operation in which a plurality of facets are combined to provide a sprite in the apparatus of [Figure 1].



[Figure 10]


 
  
[Figure 10A to 10E] are explanatory diagrams showing an operation in which a size of a sprite is enlarged in the apparatus of [Figure 1].



In [Figure 11A] , there is shown an apparatus for the control of an access to a video memory in an embodiment according to the invention. The apparatus for the control of an access to a video memory comprises an oscillator (51) for producing oscillation signals, a frequency divider (52) for dividing a frequency of the oscillation signals by a predetermined dividing ratio to produce pixel clock signals, a memory width register (3K) as already explained in [Figure 3K] having a content of a number of pixel periods dependent on a memory speed of the VRAM (7), a number of pixel periods decision circuit (53) for deciding a pixel width in accordance with the content of the memory width register (3K), means (54, 55 and 56) for producing a CPU address signal, DMA address signal and CG address signal respectively to designate addresses in an access to the VRAM (7), an address selector (57) for selecting an address at an access timing which is set by the number of pixel periods decision circuit (53), and a data latch circuit (58) for latching data read from the VRAM (7). The VRAM (7) is shown in [Figure 11A] to include a VRAM region (33) of a fictitious screen as described in [Figure 4A] and a Character Generator (34) which is also shown in [Figure 11B]. One character of the Character Generator (34) is composed of four facets CH0 Ch1, CH2 and CH3 each having 8×8 pixels by which a pattern is defined by 16 words of 8 words for the facets CH0 and CH1 and other 8 words for the facets CH2 and CH3. The characters are addressed by the first addresses of the facets CHOs shown by A0, A1, A2 . . . which are defined by character codes of background attribute tables as described in [Figures 5A and 5B].
In operation, when a horizontal display of the scanning raster number 0 is started, the VM bits of the memory width register (3K) are checked by the number of pixel periods decision circuit (53). If it is assumed that a content of the VM bits is 00, a number of pixel periods of an access to the VRAM (7) is decided to be 1 as defined in the table on page 19. Accordingly, the VRAM (7) is accessed in accordance with a CPU address signal from the CPU address signal means (54) under the control of the address selector (57) at the first pixel timing among 8 pixels of one character cycle. Next, the VRAM region (33) of the VRAM (7) is accessed at an address 0 in accordance with a CG address signal from the CG address signal means (56) at the second pixel timing. At this moment, a character code and a CG color are read from a background attribute table, as shown in [Figures 5A and 5B], of the address 0. Thereafter, accesses are performed from the CPU (2 in [Figure 1]) to the VRAM (7) at the third and fifth pixel timings except for the fourth pixel timing, and the Character Generator (34) is accessed at the sixth pixel timing. In the access to the Character Generator (34), a CG address signal of the CG address signal means (56) is determined in accordance with a pattern number corresponding to a character code which is previously checked whereby display data are read from the facets CH0 and CH1 thereof. After the seventh pixel timing, display data are further read from the facets CH2 and CH3 in accordance with the same address signal at the 8 pixel timing. As a result, one character is formed in accordance with the display data of the four facets CH0 to CH3 which are latched in the data latch circuit (58). A display of the address 0 is performed on the video display (9 in [Figure 1]) in accordance with the data thus latched in the data latch circuit (58) wherein a color of the display is determined by the CG color in the background attribute table. In the horizontal displays which follow the horizontal display of the scanning raster line 0, the same operation as explained above will be repeated.
On the other hand, if it is assumed that a content of the VM bits is 01, 10 or 11, the VRAM (7) is accessed with a number of pixel periods is 2, 2 or 4. For this reason, a content of the VM bits is determined dependent on a memory speed of the VRAM (7).
In another operation, it is assumed that a content of the VM bits is 00 in the memory width register (3K) to provide a number of pixel periods of one pixel, and that a content of the IW bits is 00 in the control register as shown in [Figure 3G] to provide an address increment width 1. An operation in which data are written into the VRAM (7) is started after the first address for writing the data is written into the memory address write register as shown in [Figure 3C]. When the VRAM (7) is accessed from the CPU (2) as shown in [Figure 12] by the indication CPU→VRAM, the data are held in the CPU read/write buffer (22 in [Figure 2A]), if the writing of the data is collided in regard to its timing with a display cycle of the VRAM (7). For this reason, the CPU (2) is released from the writing of the data as changed from 0 to 1 in regard to a timing chart of CPU→VRAM. Thereafter, when the display cycle of the VRAM (7) is finished, the data thus held in the CPU read/write buffer (22) are written, as shown by the indication VRAM WR, into the VRAM (7) at the address which is designated by the memory address write register of [Figure 3C]. At this moment, a content of the memory address write register is incremented by one. On the other hand, in a case where the VRAM (7) is accessed from the CPU (2) when data are held in the CPU read/write buffer (22), the condition WAIT becomes effective in the CPU (2) so that a wait signal is produced at the BUSY terminal connected to the control unit (20 in [Figure 2A]). Therefore, the condition WAIT is much decreased in the number of occurrences in accordance with the provision of the CPU read/write buffer (22).
In the same manner as described above, the VRAM (7) is accessed from the CPU (2) so that data are read from the VRAM as shown in [Figure 12] by the indication CPU ← VRAM. Data which are read from the VRAM (7) at an address designated by the memory address read register as shown in [Figure 3D] are once held in the CPU read/write buffer (22), when the access to the VRAM (7) is collided with the display cycle of the VRAM (7). When the display cycle of the VRAM (7) is finished, the data thus held in the CPU read/write buffer (22) are transferred to the CPU (2) as shown by the indication VRAM RD. At this moment, a content of the memory address read register is incremented by one.
Otherwise, if the CPU read/write buffer (22) is not provided, the condition WAIT is increased in the number of occurrences as shown in [Figure 13] so that a throughput of the CPU (2) is decreased. In more detail, the condition WAIT is continued in the CPU (2) until the display cycle of the VRAM (7) is finished, when the VRAM (7) is accessed from the CPU (2) for the writing of data (CPU→VRAM) and the reading thereof (CPU ← VRAM) during that cycle. When the display cycle of the VRAM (7) is finished, data are written into the VRAM (7) as shown by the indication VRAM WR, and read from the VRAM as shown by the indication VRAM RD whereby flickers are prevented from being occurred on a screen.


 
  
[Figure 11A] is a block diagram showing an apparatus for the control of an access to a video memory in an embodiment according to the invention.
  
[Figure 11B] is an explanatory diagram showing a character generator in the apparatus of [Figure 11A].
  
[Figure 12 and 13] are timing charts showing operations in the apparatus of [Figure 11A and a conventional apparatus for the control of an access to a video memory respectively.
  
[Figure 12 and 13] are timing charts showing operations in the apparatus of [Figure 11A and a conventional apparatus for the control of an access to a video memory respectively.


Claims



Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to thus limited but are to be construed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.
What is claimed is:


 An apparatus for the control of an access to a video memory comprising:
  

    
 register means for storing a number of pixel periods within a character cycle for processing the video memory.
    
 means for deciding said number of pixel periods in accordance with said content of said register means.
    
 means for addressing said video memory at timings determined in accordance with said number of pixel periods.
    
 means for latching video data read from said video memory at said timings.
  
    wherein a pattern defined by said video data is displayed on a display screen.
 An apparatus for the control of an access to a video memory according to claim 1.

    wherein said video data are read from a character generator in said video memory, and said character generator is addressed in accordance with a character code stored in a background attribute table included in said video memory.
 An apparatus for the control of an access to a video memory according to claim 2.

    wherein said character generator includes four facts which are combined to define said pattern.
 An apparatus for the control of an access to a video memory according to claim 2.

    further comprising buffer means for storing said video data which are read from said video memory during a display cycle of said video memory, said video data being stored until said display cycle of said video memory is finished.
 An apparatus for the control of an access to a video memory according to claim 1, wherein said means for deciding said number of pixel periods includes means for generating a frequency having a period equal to said pixel period.
 An apparatus for the control of an access to a video memory according to claim 5 wherein said means for generating a frequency having a period equal to said pixel period includes an oscillator circuit and a frequency divider.
 An apparatus for the control of an access to a video memory according to claim 1, wherein said means for addressing said video memory includes:
  

    
 a plurality of address registers.
    
 address selector means responsive to said means for deciding said number of pixel periods for selecting one of said address registers to be a selected address register and addressing said video memory in response to a content of said selected address register.
  
 An apparatus for the control of an access to a video memory according to claim 7, wherein said means for deciding said number of pixel periods includes means for generating a frequency having a period equal to said pixel period.
 An apparatus for the control of an access to a video memory according to claim 8, wherein said means for generating a frequency having a period equal to said pixel period includes an oscillator circuit and a frequency divider.
 An apparatus for the control of an access to a video memory comprising:
  

    
 a video memory for storing video data
    
 means for addressing said video memory
    
 buffer means for storing video data to be written into said video memory and to be read out from said video memory
    
 means for controlling said buffer means to store said video data, and producing a wait signal to suspend an accessing of said addressing means to said video memory,
  
    wherein said controlling means controls said buffer means to store said video data without producing said wait signal, when said video memory is addressed for a display cycle of said video memory,
  

    
 said controlling means controls said addressing means to access said video memory to transfer said video data stored in said buffer means when said display cycle is finished, and
    
 said controlling means generates said wait signal when said video memory is to be accessed by said addressing means during a period when said video data is stored in said buffer means.
  
 An apparatus for the control of an access to a video memory according to claim 10, wherein said video memory includes timing means for generating a frequency having a period equal to said pixel period.
 An apparatus for the control of an access to a video memory according to claim 11, wherein said timing means includes an oscillator circuit and a frequency divider.
 An apparatus for the control of an access to a video memory according to claim 10, wherein said means for addressing said video memory includes:
  

    
 a plurality of address registers.
    
 address selector means responsive to a timing signal having a frequency with a period equal to a pixel period for selecting one of said address registers to be a selected address register and addressing said video memory in response to a content of said selected address register.
  
 An apparatus for the control of an access to a video memory according to claim 13, wherein said video memory includes timing means for generating said timing signal.
 An apparatus for the control of an access to a video memory according to claim 14, wherein said timing means includes an oscillator circuit and a frequency divider.