Patent 5319786

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Patent for Multiple Screen Windows

Original Patent

In [Figure 8], there is shown an apparatus for controlling the access of VRAM (7) in a first embodiment according to the invention. The apparatus comprises a CPU (2), a raster setting register (50), a circuit (33) for producing scanning raster signals, a comparison circuit (51) including a raster counter (not shown) which counts the scanning raster signals for comparing the counted value N of the raster counter with a raster number (RN) of the raster setting register (50), and a display screen (9) which is controlled to display a background and a sprite by the CPU (2). The raster number (RN) is defined by 8 bits of 0 to 7 so that one of the raster number 0 to 255 (28 = 256) can be set therein.

In operation, the raster number (RN) of the raster setting register (50) is set to be n: as shown in [Figure 9A] by the CPU (2). The raster counter of the comparison circuit (51) counts the scanning raster signals supplied from the circuit (33). When the counted value N is equal to and larger than 0, and less than the set value n:(0 ≦ N < n1), the set value n1 is held therein. When the counted value N is equal to the set value n1, the comparison circuit (51) supplies a coincidence signal to the CPU (2) so that the raster number (RN) of the raster setting register (50) is then set to be n2 by the CPU (2) as shown in [Figure 9B]. When the counted value N is equal to and larger than n1, and less than the set value n2 (n1 < N ≦ n2), the set value n2 is held therein. When the counted value N is equal to the set value n2 is held therein. When the counted value N is equal to the set value n2, a second coincidence signal is supplied from the comparison circuit (51) to the CPU (2) so that the raster number (RN) of the raster setting register (50) is set to be n3 by the CPU (2) as shown in [Figure 9C]. In the same manner, a third coincidence signal is supplied from the coincidence circuit (51) when the counted value N is equal to the setting value n3. Upon receiving the first to third coincidence signals, the CPU (2) divides the display screen (9) into four regions in accordance with the raster numbers n1, n2 and n3. For instance, the display screen (9) is controlled to display patterns of different pages on the four divided regions by the CPU (2). Otherwise, another interruption signal may be produced when the aforementioned coincidence signal is supplied to the CPU (2).

[Figure 8] is a block diagram showing an apparatus for controlling the access of VRAM in a first embodiment according to the invention.
[Figures 9A, 9B and 9C] are explanatory diagrams showing controlling modes in the apparatus in [Figure 8]

In [Figure 10], there is shown an apparatus for controlling the access of VRAM (7) in a second embodiment according to the invention. The apparatus comprises a CPU (2), a group of registers (53), an Address Counter (52), and VRAM (7). The group of registers (53) includes a Memory Address Write Register (3C), a Memory Address Read Register (3D), a VRAM Data Write Register (3E), a VRAM Data Read Register (3F), and a Control Register (3G) as shown in [Figure 3C to 3G]. The Memory Address Write Register (3C) and the Memory Address Read Register (3D) are connected to the Address Counter (52) so that the VRAM (7) is accessed in accordance with an address value of the Address Counter (52). Data are controlled to be written into the VRAM (7) and read therefrom by the CPU (2). The Control Register (3G) includes IW bits of bits 11 and 12 defining an Increment Width along with other bits as explained in [Figure 3G]. A relation between a content of bits 11 and 12 and an Increment Width is explained at the table on page 19 so that a repeated explanation is not made here.

In a case where the IW bits are 0x00, an Increment Width is defined to be 0x01. If it is assumed that a starting address of the Memory Address Write Register (3C) is 0x00, data of the VRAM Data Write Register (3E) are written into a region of an address 0x00 of the VRAM (7) when the Address Counter (52) counts a predetermined number corresponding to the address 0x00. Then, an address of the Memory Address Write Register (3C) is incremented by 0x01 and therefore changed from 0x00 to 0x01. The data written into the VRAM (7) corresponds to data of the address 0x00 on the fictitious screen as shown in [Figure 4A]. Next, an address of the VRAM (7) is counted by the Address Counter (52) in accordance with a content 0x01 of the Memory Address Write Register (3C), and data of the VRAM Data Write Register (3E) are written into a region of an address 0x01 of the VRAM (7). In this manner, data corresponding to addresses 0x1F, 0x20 to 0x3F, 0x40 to 0x5F of horizontal directions of the fictitious screen are sequentially written into the VRAM (7).

In a case where the IW bits are 0x01, an Increment Width is defined to be 0x20. If it is assumed that a starting address of the Memory Address Write Register (3C) is 0x00 data of the VRAM Data Write Register (3E) are written into a region of an address 0x00 of the VRAM (7) when the Address Counter (52) counts a predetermined number corresponding to the address 0x00. Then, an address of the Memory Address Write Register (3C) is incremented by 0x20 and therefore changed from 0x00 to 0x20. Next, an address of the VRAM (7) is counted by the Address Counter (52) in accordance with a content 0x20 of the Memory Address Write Register (3C), and data of the VRAM Data Write Register (3E) are written into a region of an address 0x20 of the VRAM (7). In this manner, data corresponding to addresses 0x00, 0x20, 0x40, 0x60 of the fictitious screen are sequentially written into the VRAM (7). As a result, it is said that the present operation is equal to an operation in which a pattern to be displayed in horizontal directions is changed to a pattern to be displayed in vertical directions.

Otherwise, if it is assumed that an Increment Width is 0x40 or 0x80, a pattern which is enlarged by two times or four times and displayed in vertical directions is obtained. In addition, if an Increment Width is appropriately selected to be a predetermined value, an inclination, a rotation and so on of a pattern can be performed. Although the writing of data into the VRAM (7) is explained, the reading of data therefrom is also performed in the same manner as described above.

Next, an apparatus for controlling the access of VRAM (7) in a third embodiment will be explained mainly in conjunction with [Figure 2] and [Figures 3A to 3U].

In a case where the CPU (2) is a data bus width of 16 bits, a chip selecting signal 0 is supplied to the terminal CS of the Video Display Controller (1) which is thereby enabled. A data bus width signal 0 is supplied through the terminal EX 8/16 to the control unit (20) of the Video Display Controller (1).

  1. Writing of data into a register

    A register number AR of a register into which data are written is written into the Address Register (3A) (at this time, A0 = no matter, A1 = 1), and the data are written into the selected register of the register number AR (at this time, A0 = no matter, A1 = 1). As a result, data by which a function such as display modes etc. is selected and by which addresses are set for the VRAM (7) are written into registers of the Video Display Controller (1).

  2. Reading of status

    A status is read from the Status Register (3B) (at this time, A0 = no matter, A1 = 0).

  3. Writing of data into the VRAM (7)

    Following procedures are performed when data are written through the Video Display Controller (1) into the VRAM (7) by the CPU (2).

    1. The register number 0x00 of the Memory Address Write Register (3C) is written into the Address Register (3A).

    2. An address of the VRAM (7) is written into the Memory Address Write Register (3C).

    3. The register number 0x02 of the VRAM Data Write Register (3E) is written into the Address Register (3A).

    4. Data are written into the VRAM Data Write Register (3E) so that the data are written into a region of the address of the VRAM (7). Then, a content of the Memory Address Write Register (3C) is incremented by a value determined in accordance with the IW bits of the Control Register (3G).

      The procedures are repeated by the number of steps which is necessary to write a predetermined amount of data into the VRAM (7).

  4. Reading of data from the VRAM (7) Following procedures are performed when data are read through the Video Display Controller (1) from the VRAM (7) by the CPU (2).

    1. The register number 0x01 of the Memory Address Read Register (3D) is written into the Address Register (3A).

    2. An address of the VRAM (7) is written into the Memory Address Read Register (3D).

    3. The register number 0x03 of the VRAM Data Read Register (3F) is written into the Address Register (3A).

    4. Data are written into the VRAM Data Read Register (3F) so that the data are read from a region of the address of the VRAM (7). Then, a content of the Memory Address Read Register (3D) is incremented by a value determined in accordance with the IW bits of the Control Register (3G).

On the other hand, in a case where the CPU (2) is a data bus width of 8 bits, a chip selecting signal 0 is supplied to the terminal CS of the Video Display Controller (1) which is thereby enabled. A data bus width signal 1 is supplied through the terminal EX 8/16 to the control unit (20) of the Video Display Controller (1).

  1. Writing of data into a register
    1. A register number AR of a register into which data are written is written into the Address Register (3A) (at this time, A0 = 0, A1 = 1).

    2. A lower byte of the data is written into the selected register of the register number AR (at this time, A0 = 0, A1 = 1).

    3. An upper byte of the data is written into the selected register (at this time, A0 = 1, A1 = 1).

  2. Reading of status

    A lower byte of status data is read from the Status Register (3B), while an upper byte of 0x00 is read therefrom.

  3. Writing of data into the VRAM (7)

    Procedures of an 8 bit data bus width are basically the same as those of a 16 bit data bus width as described before, provided that a lower byte of data and an upper byte thereof are sequentially processed when an address is written into the Memory Address Write Register (3C) and data are written into the VRAM Data Write Register (3E). At this time, an address of the Memory Address Write Register (3C) is incremented by a value determined in accordance with the IW bits of the Control Register as described before.

  4. Reading of data from the VRAM (7)

    This is also the same as in a 16 bit data bus width, provided that a lower byte of data and an upper byte thereof are sequentially processed.

    The writing of data into the VRAM (7) will be described in more detail. At first, the register number 0x00 of the Memory Address Write Register (3C) is written into the Address Register (3A). Next, a starting address for the writing of data is divided into a lower byte and an upper byte which are written into the Memory Address Write Register (3C) in a sequential order of the upper byte after the lower byte. Thereafter, a lower byte of data is written into the VRAM data write register, and an upper byte of the data is then written thereinto. Upon the writing of the upper byte, a content of the Memory Address Write Register (3C) is incremented by a value determined in accordance with the IW bits of the Control Register (3G).

    In this manner, an image is displayed on a display screen of a television (9) under a selected one of a 16 and 8 bit data bus widths. In more detail, an address of the Sprite Attribute Table (31) or the Background Attribute Table (31) in the VRAM (7) is designated by the address unit (21) so that the Sprite Generator (32) or the character generator in the VRAM (7) is accessed in accordance with a pattern number, a display position (X, Y), a color code etc. of a sprite and a character code etc. of a background. Data read from the sprite generator or the character generator thus accessed are stored in the Sprite Shift Register (24) or the Background Shift Register (25). These data of the Sprite Shift Register (24) or Background Shift Register (25) are supplied through the priority circuit (28) to the Video Color Encoder (3). At this stage, pattern signals of a sprite or a character are passed through the terminals VD0 to VD3, and color codes are passed through the terminals VD4 to VD7. The terminals SP/BG is high when a sprite information is passed through these terminals, and low when a background information is passed therethrough. The priority circuit (28) gives a priority to one of a sprite and a background in accordance with a bit SP/BG of a sprite attribute table. The Video Color Encoder (3) which is supplied with the pattern signals produces RGB analog signals or video color signals.

    Further, an apparatus for controlling the access of VRAM (7) in a fourth embodiment according to the invention will be explained.

    At first, the register number 0x0F of the DMA Control Register (3Q) is written into the Address Register (3A). It is assumed that a control mode in which bit 2 of SI/D and bit 3 of DI/D are 0x00 respectively is set in the DMA Control Register (3Q). Next, the register number 0x10 of the DMA Source Address Register (3R) is written into the Address Register (3A) thereby writing a starting address of a source address in a DMA transfer into the DMA source Address Register (3A), and the register number 0x11 of the DMA destination Address Register (3S) is written into the Address Register (3A) thereby writing a starting address of a destination address in the DMA transfer. In addition, the register number 0x12 of the DMA Block Length Register (3T) is written into the Address Register (3A) thereby writing a block length of the DMA transfer into the DMA Block Length Register (3T). At this time, if an interface of the CPU (2) is of a 16 bit data bus width, a lower byte and an upper byte of the block length are written thereinto simultaneously. This is trigger for the commencement of a DMA transfer so that data are transferred directly from the source address of the VRAM (7) to the destination address thereof. On the other hand, if an interface of the CPU (2) is of an 8 bit data bus width, a lower byte of the block length is firstly written into the DMA Block Length Register (3T), and an upper byte thereof is then written thereinto. The setting of the upper byte is a trigger for the commencement of the DMA transfer.

In the DMA transfer as described above, the source and destination addresses are incremented in the DMA Source Address Register (3R) and DMA destination Address Register (3S) by one in accordance with the content 0x00 of the bits 2 and 3 of the DMA Control Register (3Q). At the same time, a counting up or down is performed in a counter for counting the block length. When a counted value is equal to the block length, the DMA transfer is controlled to be finished.

Although the DMA transfer is explained to be performed between two regions of the VRAM (7), it may be performed between the VRAM (7) and the Sprite Attribute Table buffer (23). In such a case, a starting address of a source address is defined in accordance with a content of the DMA VRAM-SATB Source Address Register (3U).

[Figure 10] is a block diagram showing an apparatus for controlling the access of VRAM in a second embodiment according to the invention.