Patent VDC Registers

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|- class="figures_and_drawings_fixed" | In [Figures 3A to 3U], there are shown various kinds of registers included in the Control Unit (20) of the Video Display Controller (1). (a) Address Register ([Figure 3A]) A register number AR is exclusive written into the address register designating one of the memory address write register to DMA VRAM-SATB source address register as shown in [Figures 3C to 3U] so that data are writing into the Video Display Controller (1) under the condition that the A1 and CS terminals thereof are Low. In a case where 16 bit data bus is selected, the EX 8/16 terminal is 0, the A1 terminal is 0, the R/W terminal is W, and the A0 terminal is no matter. In a case where 8 bit data bus is selected, the EX 8/16 terminal is 1, the A0 and A1 terminals are 0, and the R/W terminal is W.

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[Figure 3A] Address Register (AR)

|- class="figures_and_drawings_fixed" | (b) Status Register ([Figure 3B]) A bit corresponding to one of interruption jobs is set to be High in the status register to make the interruption active when a cause of the interruption which is enabled by an interruption permission bit of a Control Register and DMA Control Register as showing in [Figures 3G and 3Q] is occurred. When the status is read from the status register, the corresponding bit is cleared automatically. The status indicating bits are as follows. (1) bit 0 (CR) - collision of sprites It is indicated that the sprite number 0 of a sprite is collided with any one of the sprite numbers 1 to 63 of sprites. (2) bit 1 (OR) - more sprites than a predetermined number (2.1) a case where more than 17 sprites are detected on a single raster line. (2.2) a case where data of a sprites which is designated are not transferred to a data buffer in a horizontal trance period. (2.3) a case where a bit of CGX in control data of a sprite by which two sprites are joined in a horizontal direction is set so that data of the sprites are not transferred to a data buffer. (3) bit 2 (PR) - detection of raster It is indicated that a value of a raster counter becomes a predetermined value of a raster detecting register. (4) bit 4 (DS) - finishing of DMA transfer It is indicated that data transfer between the VRAM (7) and Sprite Attribute Table buffer (23) is finished. (5) bit 4 (DV) - finishing of DMA transfer It is indicated between two regions of VRAM (7) is finished. (6) bit 5 (VD) - vertical retrace period It is indicated that the VRAM (7) accessed for the writing or reading of data by the CPU (2) so that the BUSY terminals is 0.

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[Figure 3B] Status Register (SR)

|- class="figures_and_drawings_fixed" | (c) Memory Address Write Register (register name 0x00, [Figure 3C]) A starting address MAWR is written into the memory address write register so that the writing of data begins at the starting address of the VRAM (7).

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[Figure 3C] Memory Address Write Register (MAWR)

|- class="figures_and_drawings_fixed" | (d) Memory Address Read Register (register number 0x01, [Figure 3D]) A starting address MARR is written into the memory address read register. When the upper byte of the starting address is written thereinto, data are begun to be read from the starting address of the VRAM (7) so that data thus read are written into a VRAM data read register as showing in [Figure 3F]. There after, the starting address MARR is automatically incremented by one.

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[Figure 3D] Memory Address Read Register (MARR)

|- class="figures_and_drawings_fixed" | (e) VRAM Data Write Register (register number 0x02, [Figure 3E]) Data which are transferred from the CPU (2) to the VRAM (7) are written into the VRAM data write register. When the upper byte of the data VWR is written thereinto, the Video Display Controller (1) begins to write the data into the VRAM (7) and the address MAWR of the memory address write register is automatically incremented by one upon writing of the data.

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[Figure 3E] VRAM Data Write Register (VWR)

|- class="figures_and_drawings_fixed" | (f) VRAM Data Read Register (register number 0x02, [Figure 3F]) Data which are transferred from the VRAM (7) to the CPU (2) are written into the VRAM data read register. When the upper byte of the data VRR is read therefrom, the reading of data is performed at the following address of the VRAM (7).

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[Figure 3F] VRAM Data Read Register (VRR)

|- class="figures_and_drawings_fixed" | (g) Control Register (register number 0x05, [Figure 3G]) An operating mode of the Video Display Controller (1) is controlled in accordance with the following bits of the Control Register. (1) bits 0 to 3 (IE) - enable of interruption request (1.1) bit 0 - collision detection of sprites (1.2) bit 1 - excess number detection of sprites (1.3) bit 2 - raster detection (1.4) bit 3 - detection of vertical retrace period (2) bits 4 and 5 (EX) - external synchronization US4951038-chart1.png (3) bit 6 (SB) - sprite blanking It is decided whether a sprite should be displayed on a screen or not. The control of the bit is effective in the following Horizontal Display Period. (3.1) 0 - blanking of a sprite (3.2) 1 - display of a sprite (4) bit 7 (BB) - background blanking It is decided whether background should be displayed on a screen or not. The control of the bit is effective in the following Horizontal Display Period. (4.1) 0 - blanking of background (4.2) 1 - display of background. (3.4) As a result, when bits 6 and 7 are both 0, there is a resulted "burst mode" in which the following operations can be performed. (3.4.1) The access to the VRAM (7) is not performed for a display, but the VRAM (7) is accessed by the CPU (2). (3.4.2) DMA between two regions of the VRAM (7) is possible to be performed at any time. In such occasions, the terminals VD0 and VD7 are all Low while the SP/BG terminal is High. On the other hand, when the bits 6 and 7 are both 1, there is released from the "burst mode". (5) bits 8 and 9 (TE) - selection of DISP terminal outputs US4951038-chart3.png (6) bit 10 (DR) - dynamic RAM refresh Refresh address is supplied from the terminals MA0 to MA15 upon the setting of the bit in a case where VRAM pixel width is of 2 pixels or 4 pixels for background in a memory width register as showing in [Figure 3K]. (7) bits 11 and 12 (IW) - increment width selection of memory address write register or memory address read register A width which is incremented in address is selected as follows. US4951038-chart2.png In a case of 8 bit access, an address is incremented upon the upper byte.

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[Figure 3G] Control Register (CR)

|- class="figures_and_drawings_fixed" | (h) Raster Detecting Register (register number 0x06, [Figure 3H]) A raster number RCR at which an interruption job is performed is written into the raster detecting register. An interruption signal is produced when a value of a raster counter is equal to the raster number RCR. The raster counter is preset to be 64 at a preceding scanning raster line to a display starting raster line as described in more detail later, and is increased at each raster line by one.

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[Figure 3H] Raster Detecting Register (RDR)

|- class="figures_and_drawings_fixed" | (i) BGX Scroll Register (register number 0x07, [Figure 3I]) The BGX scroll register is used for a horizontal scroll of background on a screen. When a content BXR is rewritten therein, the content is effective in the following raster line.

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[Figure 3I] BGX Scroll Register (BGX)

|- class="figures_and_drawings_fixed" | (j) BGY Scroll Register (register number 0x08, [Figure 3J]) The BGY scroll register is used for a vertical scroll of background on a screen. When a content BYR is rewritten therein, the content is effective to be as "BYR + 1" in the following raster line.

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[Figure 3J] BGY Scroll Register (BGY)

|- class="figures_and_drawings_fixed" | (k) Memory Width Register (register number 0x09, [Figure 3K]) (1) bits 0 and 1 (VM) - VRAM pixel width A pixel width in which an access to the Background Attribute Table and character generator, DMA and access of the CPU (2) to the VRAM (7) during a horizontal display period are performed is written into the bits of the memory width register. The pixel width is decided dependent on a memory speed of the VRAM (7). When the bits 0 and 1 are re-written therein, the content is effective at the beginning of a vertical retrace period. US4951038-chart4.png BAT is for Background Attribute Table, and CG is for character generator. (2) bits 2 and 3 (SM) - sprite pixel width A pixel width which an access to the sprite generator is performed during a horizontal retrace period is written into the bits of the memory width register. US4951038-chart5.png (3) bits 4 to 6 (SCREEN) The number of character in X and Y directions of a fictitious screen is decided dependent on the content of the bits. When a content is effective at the beginning of a vertical retrace period. US4951038-chart7.png (4) bit 4 (CM) - CG mode When a VRAM pixel width is of 4 pixels, a color block of a character generator is changed dependent on the bit. A content is writtent into the bit, the content is effective in the following raster line.

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[Figure 3K] Memory Width Register (MWR - not to be confused with terminal MWR)

|- class="figures_and_drawings_fixed" | (l) Horizontal Synchronous Register (register number 0x0A, [Figure 3L]) (1) bits 1 to 4 (HSW) - horizontal synchronous pulse A pulse width of Low level of a horizontal synchronous pulse is set as an unit of a character cycle. One of 1 to 32 is selected by using 5 bits to comply with the specification of a video display. (2) bits 8 to 14 (HDS) - starting position of horizontal display A period between a rising edge of a character cycle. An optimum position in a horizontal direction on a video display is decided by a content of the 7 bits. When it is assumed that a horizontal display position (horizontal back porch) is N, N - 1 is written into HDS bits.

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[Figure 3L] Horizontal Synchronous Register (HSR)

|- class="figures_and_drawings_fixed" | (m) Horizontal Display Register (register number 0x0B, [Figure 3M]) (1) bits 0 to 6 (HDW) - horizontal display width A display period in each raster line is set as an unit of a character cycle, and is decided in accordance with the number of characters in the horizontal direction on a video display dependent on a content of the 7 bits. If it is assumed that a horizontal display position is N, N - 1 is written into HDW bits. (2) bits 8 to 11 (HDE) - horizontal display ending position A period between an ending of a Horizontal Display Period and a rising edge of a horizontal synchronous signal is set as an unit of a character cycle. An optimum position of a horizontal display is set on a video display by the 7 bits. When it is assumed that a horizontal display ending position (horizontal back porch) is N, N -1 is written into HDE bits.

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[Figure 3M] Horizontal Display Register (HDR)

|- class="figures_and_drawings_fixed" | (n) Vertical Synchronous Register (register number 0x0C, [Figure 3N]) (1) bits 0 to 4 (VSW) - vertical synchronous pulse width A pulse width of a vertical synchronous signal is decided in a width of Low level as a unit of a raster line. One of 1 to 32 is selected to comply with a specification of a video display. (2) bits 8 to 15 (VDS) - vertical display starting position A period between a rising edge of a vertical synchronous signal and a vertical synchronous starting position is set as an unit of a raster line. When it is assumed that a vertical display starting position (vertical back porch) is N, N-2 is written into the bits.

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[Figure 3N] Vertical Synchronous Register (VSR)

|- class="figures_and_drawings_fixed" | (o) Vertical Display Register (register number 0x0D, [Figure 3O]) A vertical display period (display region) is set as an unit of a raster line. A vertical display width is decided in accordance with the number of raster lines to be displayed on a video display which is defined by a content of the 9 bits. When it is assumed that a vertical display width is N, N - 1 is written into the VDW bits.

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[Figure 3O] Vertical Display Register / Vertical Display Width (VDW)

|- class="figures_and_drawings_fixed" | (p) Vertical Display Ending Position Register (register number 0x0E, [Figure 3P]) A period between a vertical display ending position and a rising edge of a vertical synchronous signal is set as an unit of a raster line. When it is assumed that a vertical optimum position (vertical front porch) is N to be defined by the 8 bits, N is written into the VCR bits.

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[Figure 3P] Vertical Display Ending Position Register / Vertical C..... R..... (VCR)

|- class="figures_and_drawings_fixed" | (q) DMA Control Register (register number 0x0F, [Figure 3Q]) (1) bit 0 (DSC) - Enable an interruption at the finishing of transfer between the VRAM (7) and Sprite Attribute Table buffer (23). It is decided whether or not an interruption is enabled at the finishing time of the transfer. (1.1) 0 - disable (1.2) 1 - enabled (2) bit 1 (DVC) - Enable an interruption at the finishing of transfer between two regions of the VRAM (7). It is decided whether or not an interruption is enabled finishing time of the transfer. (2.1) 0 - disable (2.2) 1 - enabled (3) bit 2 (SI/D) - Increment/decrement of a source address One of automatically increment and decrement of a source address is selected in a transfer between two regions of VRAM (7). (3.1) 0 - increment (3.2) 1 - decrement (4) bit 3 (DI/D) - Increment/decrement of a destination address One of automatically increment and decrement of a destination address is selected in a transfer between two regions of VRAM (7). (4.1) 0 - increment (4.2) 1 - decrement (5) bit 4 (DSR) - repetition of a transfer between the VRAM (7) and the Sprite Attribute Table buffer (23) is enabled. (5.1) 0 - disable (5.2) 1 - enabled

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[Figure 3Q] DMA Control Register (DCR)

|- class="figures_and_drawings_fixed" | (r) DMA Source Address Register (register number 0x10, [Figure 3R]) A starting address of a source address is allocated in a transfer between two regions of the VRAM (7).

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[Figure 3R] DMA Source Address Register (SOUR)

|- class="figures_and_drawings_fixed" | (s) DMA Destination Address Register (register number 0x11, [Figure 3S]) A starting address of a destination address is allocated in a transfer between two regions of the VRAM (7).

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[Figure 3S] DMA Destination Address Register (DESR)

|- class="figures_and_drawings_fixed" | (t) DMA Block Length Register (register number 0x12, [Figure 3T]) A length of a block is defined in a transfer between two regions of the VRAM (7).

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[Figure 3T] DMA Block Length Register (LENR)

|- class="figures_and_drawings_fixed" | (u) DMA VRAM-SATB Source Address Register (register number 0x13, [Figure 3U]) A starting address of a source address is allocated in a transfer between the VRAM (7) and Sprite Attribute Table buffer (23).

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[Figure 3U] DMA VRAM-SAT Source Address Register (DVSSR)