Difference between revisions of "HuC6270"
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[[Image:HuC6270-Circuit.png | thumb | 832px | HuC6270 Circuit]] | [[Image:HuC6270-Circuit.png | thumb | 832px | HuC6270 Circuit]] | ||
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Latest revision as of 04:00, 7 November 2015
|
Video Display controller (VDC). Referred to as "7UP" by NEC-HE. Notes:
Contents
Specifications
Interface
Address | Access | Description
(Mapped | mode |
to $FF) | |
--------------+--------+---------------------------------------------------
$0000 | R | 6270 Status register
| |
| | Different bits flag different conditions.
| | Not all are known.
| | (Note: can use special ST0 opcode to store
| | an immediate value.)
| | b 7 = 0
| | b 6 = 'BSY' flag
| | I believe this is '1' when a DMA transfer
| | is happening
| | b 5 = 'VD' flag
| | I believe this is a '1' when Vertical Sync
| | happens, otherwise a '0' (uncertain)
| | b 4 = 'DV' flag (unknown)
| | b 3 = 'DS' flag (unknown)
| | b 2 = 'RR' flag
| | Set during a Scanline interrupt (see RCR
| | register)otherwise '0'
| | b 1 = 'OR' flag (unknown)
| | b 0 = 'CR' flag (unknown)
| |
$0000 | W | 6270 Address register
| |
| | b 7-5 = ignored
| | b 4-0 = 6270 register number to access using
| | the 6270 data registers
| | ($0002 and $0003). Please see 6270
| | register list (SECTION 4) for details.
| |
$0002 | R/W | 6270 data LSB
| |
| | Note: can use special ST1 opcode to store
| | an immediate value.)
| |
$0003 | R/W | 6270 data MSB
| |
| | Note: can use special ST2 opcode to store
| | an immediate value.)
--------------+--------+---------------------------------------------------
Status Register A bit corresponding to one of interruption jobs is set to be "H" in the status register
to make the interruption active when a cause of the interruption which is enabled by an
interruption permission bit of a control register and DMA control register as showing in
Figures 3G and 3Q is occurred. When the status is read from the status register, the
corresponding bit is cleared automatically.
The status indicating bits are as follows. Read Behavior
Write Behavior
Address Register A register number "AR" is exclusive written into the address register designating one of
the memory address write register to DMA VRAM-SATB source address register as shown in
Figures 3C to 3U so that data are writing into the video display controller(1) under the
condition that the A1 and CS terminals thereof are "L".
In a case where 16 bit data bus is selected, the EX 8/16 terminal is "0", the A1
terminal is "0", the "R/W" terminal is "W", and the A0 terminal is no matter.
In a case where 8 bit data bus is selected, the EX 8/16 terminal is "1", the A0
and A1 terminals are "0", and the "R/W" terminal is "W".
Data RegisterRead/Write register. Data in the VDC register selected/indexed by the Status Register. VRAM Registers$00 - MAWR - Memory Address Write Register (VRAM Write Address) A starting address "MAWR" is written into the memory address write register so that the
writing of data begins at the starting address of the VRAM(7).
MAWR specifies a word offset into VRAM for writing. Subsequent writes to register $02 (VWR) will store data at the offset specified by MAWR. After each write, MAWR is incremented by the amount specified in the IW bits of CR. MAWR wraps back to zero when it's value exceeds $FFFF. The LSB and MSB of MAWR can be updated independently of each other; accessing either half directly updates the MAWR register rather than any temporary storage. This allows quick non-sequential addressing of VRAM without having to set the entire address every time. $01 - MARR - Memory Address Read Register (VRAM Read Address) A starting address "MARR" is written into the memory address read register. When the
upper byte of the starting address is written thereinto, data are begun to be read from
the starting address of the VRAM(7) so that data thus read are written into a VRAM data
read register as showing in Figure 3F. There after, the starting address "MARR" is
automatically incremented by one.
MARR specifies a word offset into VRAM for reading. When the MSB is written, VRAM data from the current offset is transferred into a read buffer, and then MARR is incremented by the amount specified in the IW bits of CR. For any following VRR reads, the buffered value is immediately returned and this process repeats; the buffer is loaded from data at the current offset and MARR is incremented again. The LSB of MARR can be updated independently of the MSB. This does not cause the buffer to be loaded, only a write to the MSB will do that. $02 - VRR - VRAM Data Read Register A starting address "MARR" is written into the memory address read register. When the
upper byte of the starting address is written thereinto, data are begun to be read from
the starting address of the VRAM(7) so that data thus read are written into a VRAM data
read register as showing in Figure 3F. There after, the starting address "MARR" is
automatically incremented by one.
Reading the LSB of VRR returns the LSB of the read buffer. Reading the MSB returns the MSB of the read buffer immediately, then loads the buffer with VRAM from the current offset MARR represents and increments MARR by the value specified by the IW bits of CR. To read only the MSB of multiple words, the MSB of VRR can be repeatedly read instead of reading both the LSB and MSB. Note: when reading from VDC addresses $0002 or $0003 when VRR is not selected, the buffer will not be reloaded nor will MARR increment when the MSB is read. The buffer contents will always return the last-loaded value but never update. $02 - VWR - VRAM Data Write Register Data which are transferred from the CPU(2) to the VRAM(7) are written into the VRAM data
write register. When the upper byte of the data "VWR" is written thereinto, the video
display controller(1) begins to write the data into the VRAM(7) and the address "MAWR" of
the memory address write register is automatically incremented by one upon writing of the
data.
When writing to VWR, the LSB is stored in a latch rather than VRAM. Any additional writes to the LSB only update the latch contents and do not affect VRAM. When the MSB is written to, the latched LSB and new MSB data are stored to VRAM at the current offset specified by MAWR. By loading the LSB with a given value and writing to the MSB repeatedly, you can fill VRAM with a constant LSB value and variable MSB value. $05 - CR - Control Register
$06 - RCR - Raster Counter Register A raster number "RCR" at which an interruption job is performed is written into the
raster detecting register. An interruption signal is produced when a value of a raster
counter is equal to the raster number "RCR". The raster counter is preset to be "64" at
a preceding scanning raster line to a display starting raster line as described in more
detail later, and is increased at each raster line by one.
A raster number "RCR" at which an interruption job is performed is written into the raster detecting register. An interruption signal is produced when a value of a raster counter is equal to the raster number "RCR". The raster counter is preset to be "64" at a preceding scanning raster line to a display starting raster line as described in more detail later, and is increased at each raster line by one. $07 - BXR - Background X-Scroll Register The BGX scroll register is used for a horizontal scroll of background on a screen. When
a content "BXR" is rewritten therein, the content is effective in the following raster
line.
The value written to BXR is latched on each scanline, preventing mid-scanline changes to BXR. Further changes to BXR will not change the display until the next scanline is displayed. When the VDC generates synchronization signals this duration is in units of VDC scanlines, and when the VDC inputs external synchronization signals this is in units of VCE scanlines. For example if the VDC displays multiple VDC scanlines in one VCE scanline, the same BXR value applies to all VDC scanlines until the current VCE scanline ends. $08 - BYR - Background Y-Scroll Register The BGY scroll register is used for a vertical scroll of background on a screen. When a
content "BYR" is rewritten therein, the content is effective to be as "BYR+1" in the
following raster line.
The value written to BYR is latched on each scanline, preventing mid-scanline changes to BYR. Further changes to BYR will not change the display until the next scanline is displayed. When the VDC generates synchronization signals this duration is in units of VDC scanlines, and when the VDC inputs external synchronization signals this is in units of VCE scanlines. For example if the VDC displays multiple VDC scanlines in one VCE scanline, the same BYR value applies to all VDC scanlines until the current VCE scanline ends. $09 - MWR - Memory Width RegisterCharacter cyclesThe fundamental unit of time observed by the VDC is the duration of one pixel clock cycle. The pixel clock is output by the VCE and can be any of the following:
The VDC accesses VRAM in groups called character cycles. Each character cycle can be split into eight slots, which have a duration of one pixel clock each. The actual VRAM read or write cycle spans one or more slots, selectable in units of 1, 2, or 4 slots each. Here's a diagram showing the number of VRAM accesses that can be made in one character cycle depending on number of slots allocated to read or write cycle:
Within the same period of time a character cycle spans, up to 8 accesses can be done when the VRAM access cycle width is 1 slot, 4 accesses can be done when cycle width is 2 slots, and only two access can be done when the cycle width is 4 slots. The PCE uses 100ns SRAM chips as it's video RAM, so the only situation that is problematic is using a 1-cycle pixel width along with the 10.738635 MHz pixel clock. In this case each cycle is ~93 ns which violates the minimum access time requirements of the SRAM. In practice this does not cause any problems, however it does mean operating the memory 7% faster than it's guaranteed to work. This can be remedied by using a pixel width mode with longer cycles. VRAM pixel widthThe VDC will make as many sequential character cycles as the screen is wide as specified in the HDW field plus two, regardless of any horizontal scroll setting. These occur back-to-back in realtime as the display is rendered (I think there is a 1 or 2 character pipeline before any pixels are actually output). For example if the screen is 32 characters wide, 34 character cycles occur. Bits 1, 0 of MWR set the VRAM access cycle grouping, referred to as the 'VRAM pixel width'. Bit 7 sets the character generator read mode when only two of four bitplanes can be read, due to insufficient VRAM access cycles available. Bits 1-0 : VRAM pixel width.
The first three modes function identically. The last mode only has enough spare time in each character cycle to read CG0 or CG1, but not both. Selection of either bitplane group is done by the character generator mode bit (CM), which is bit 7 of MWR. It specifies 0= CG0 or 1= CG1. Internally, the VDC assumes the missing bitplane data is forced to zero. This means that tiles displayed when CM=0 use colors 0,1,2,3, and tiles displayed when CM=1 use colors 0,4,8,C. Sprite pixel widthDuring the horizontal blanking period, the VDC fetches character generator data for the sprites (up to 16) that passed y-evaluation and have their respective data buffered in the VDC's on-chip sprite storage. The bitplane data is loaded into shift registers and will be output serially during the next scanline. The duration of the fetch period directly relates to how much horizontal blanking time is available, as defined by the HSW, HDS, HDW, and HDE registers. If the period is too short, the process is aborted. It seems the sprites that weren't loaded have their shift registers reset to zero, as previously loaded sprite data or garbage data is not shown (this needs more testing). Much like background rendering, bits 3-2 of MWR set the character cycle allocation for sprites, referred to as the 'Sprite pixel width'. Bits 3-2 : Sprite pixel width.
Bit 0 of the pattern code field of each sprite entry specifies which bitplanes are read for a sprite pixel width setting of 11b. It can be 0= SP0,SP1 or 1= SP2,SP3. The unused bitplanes are forced to zero so that the colors used out of a 16-color palette are 0,1,2,3 when SP0,SP1 are read, or 0,4,8,C when SP2,SP3 are read. Display Registers$0A - HPR - Horizontal Synchronous Register (1) bits 1 to 4 (HSW) - horizontal synchronous pulse
A pulse width of "L" level of a horizontal synchronous pulse is set as an unit of a
character cycle. One of 1 to 32 is selected by using 5 bits to comply with the
specification of a CRT display.
(2) bits 8 to 14 (HDS) - starting position of horizontal display
A period between a rising edge of a character cycle. An optimum position in a
horizontal direction on a CRT display is decided by a content of the 7 bits. When
it is assumed that a horizontal display position (horizontal back porch) is "N",
"N-1" is written into HDS bits.
Bits 4-0 : Horizontal Sync Width (HSW) HSW defines the width of the horizontal sync pulse in 8-pixel (character) units. The range is 1 to 32 characters. HDS defines the interval after the horizontal sync pulse to the start of the horizontal display period in character units. The range is 1 to 128 characters.
This distinction is important; increasing values of HSW do not displace the horizontal display area immediately following an external HSYNC pulse, but they will for all subsequent VDC-generated scanlines before /HSYNC occurs again. $0B - HDR - Horizontal Display Register (1) bits 0 to 6 (HDW) - horizontal display width
A display period in each raster line is set as an unit of a character cycle, and is
decided in accordance with the number of characters in the horizontal direction on a
CRT screen dependent on a content of the 7 bits. If it is assumed that a horizontal
display position is "N", "N-1" is written into HDW bits.
(2) bits 8 to 11 (HDE) - horizontal display ending position
A period between an ending of a horizontal display period and a rising edge of a
horizontal synchronous signal is set as an unit of a character cycle. An optimum
position of a horizontal display is set on a CRT display by the 7 bits. When it is
assumed that a horizontal display ending position (horizontal back porch) is "N",
"N-1" is written into HDE bits.
Bits 6-0 : Horizontal Display Width (HDW) HDW defines the width of the horizontal active display period in character units. The range is 1 to 128 characters. HDE defines the interval following HDE to the end of the scanline, at which poinst the HSW state is entered and a horizontal sync pulse is generated. The range is 1 to 128 characters. It should be set to the remainder from the desired number of characters per scanline, minus HSW, HDS, and HDW. $0C - VSR - Vertical Synchronous Register (1) bits 0 to 4 (VSW) - vertical synchronous pulse width
A pulse width of a vertical synchronous signal is decided in a width of "L" level
as a unit of a raster line. One of 1 to 32 is selected to comply with a
specification of a CRT display.
(2) bits 8 to 15 (VDS) - vertical display starting position
A period between a rising edge of a vertical synchronous signal and a vertical
synchronous starting position is set as an unit of a raster line. When it is assumed
that a vertical display starting position (vertical back porch) is "N", "N-2" is
written into the bits.
$0D - VDR - Vertical Display Register A vertical display period (display region) is set as an unit of a raster line. A
vertical display width is decided in accordance with the number of raster lines to be
displayed on a CRT display which is defined by a content of the 9 bits. When it is
assumed that a vertical display width is "N", "N-1" is written into the VDW bits.
$0E - VCR - Vertical Display Ending Postition Register A period between a vertical display ending position and a rising edge of a vertical
synchronous signal is set as an unit of a raster line. When it is assumed that a
vertical optimum position (vertical front porch) is "N" to be defined by the 8 bits,
"N" is written into the VCR bits.
Bits 7-0 : Vertical Display Position End (VCR) VCR defines the interval following VDW to the end of the frame, at which point the VSW state is entered and a vertical sync pulse is generated. The range is 0 to 255 scanlines. It should be set to the remainder from the desired number of scanlines per frame, minus VSW, VDS, and VDW. When the VDC inputs external synchronization signals, VCR should be set to a value equal to or larger than the number of scanlines the hardware generates from one edge of /VSYNC to the next. Otherwise the VDC will start generating another frame within the current display frame. This can be used to arbitrarily force additional VD interrupts and VRAM to SAT DMA transfers within a single VCE-defined frame. DMA Registers$0F - DCR - DMA Control Register (1) bit 0 (DSC) - enable and interruption at the finishing of transfer between the
VRAM(7) and sprite attribute table buffer (23)
It is decided whether or not an interruption is enabled at the finishing time of
the transfer.
(1.1) "0" - disable
(1.2) "1" - enabled
(2) bit 1 (DVC) - enable of interruption at the finishing of transfer between two
regions of the VRAM(7).
It is decided whether or not an interruption is enabled finishing time of the
transfer
(2.1) "0" - disable
(2.2) "1" - enabled
(3) bit 2 (SI/D) - increment/decrement of a source address
One of automatical increment and decrement of a source address is selected in a
transfer between two regions of VRAM(7).
(4.1) "0" - disable
(4.2) "1" - enabled
(5) bit 5 (DSR) - repetition of a transfer between the VRAM(7) and the sprite
attribute table buffer(23) is enabled.
$10 - SOUR - Source Address Register A starting address of a source address is allocated in a transfer between two regions
of the VRAM(7).
$11 - DESR - DMA Destination Address Register A starting address of a destination address is allocated in a transfer between two
regions of the VRAM(7).
$12 - LENR - DMA Block Length RegisterA length of a block is defined in a transfer between two regions of the VRAM(7). $13 - SATB - Sprite Attribute Table Address RegisterThe address of the Sprite Attribute Table. This is the only address used for access to the SATB. VRAM AccessTypically when loading large amounts of data into VRAM the screen is turned off for several frames. In most video hardware turning the screen off stops display related DMA and gives the CPU full access to VRAM. The VDC handles things a bit differently. BURST mode is when the color bus outputs $0100 on VD8-VD0 (sprite palette #0, color #0), display DMA is stopped (no fetching of BAT data, background patterns, sprite patterns), and the CPU has unrestricted access to VRAM regardless of the MWR settings. BURST mode is enabled in two situations: 1. Any display state outside of VDW is considered to be in the BURST mode. A possible exception is that display DMA needs to be done on line 262 or 263 (depending on the frame height) for graphics to be displayed on scanline 0. 2. If bits 7 and 6 of CR are reset prior to VDW occurring, BURST mode is forcibly entered for the entire duration of VDW. Any changes to bits 7 and 6 have no effect until the next transition into VDW, at which point they are sampled again. Note that this means simply turning off the background and/or sprites during VDW does *not* select BURST mode, and VRAM access is still restricted. When the background is turned off during the display, the color bus outputs $0000 on VD8-VD0 (background palette #0, color #0). To maximize VRAM throughput, it isn't necessary to force a BURST-in-VDW display condition. The duration of VDW can just be shortened to letterbox the screen and allocate more scanlines to to the other display periods, giving more BURST time. A MWR setting of $00 gives the CPU the largest amount of access cycles (twice per 8 pixels) which seems to be exactly equal to the amount of accesses available during BURST mode. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin assignments
| Pin | Signal | Direction | Description |
|---|---|---|---|
| 1 | CS | in | VDC chip select |
| 2 | RD | in | Write strobe |
| 3 | WR | in | Read strobe |
| 4 | D15 | in / out | Data bus, bit 15 |
| 5 | D14 | in / out | Data bus, bit 14 |
| 6 | D13 | in / out | Data bus, bit 13 |
| 7 | D12 | in / out | Data bus, bit 12 |
| 8 | D11 | in / out | Data bus, bit 11 |
| 9 | D10 | in / out | Data bus, bit 10 |
| 10 | D9 | in / out | Data bus, bit 9 |
| 11 | GND | s | Ground (VSS1) |
| 12 | D8 | in / out | Data bus, bit 8 |
| 13 | D7 | in / out | Data bus, bit 7 (16 bit mode) |
| 14 | D6 | in / out | Data bus, bit 6 (16 bit mode) |
| 15 | D5 | in / out | Data bus, bit 5 (16 bit mode) |
| 16 | D4 | in / out | Data bus, bit 4 (16 bit mode) |
| 17 | D3 | in / out | Data bus, bit 3 (16 bit mode) |
| 18 | +5V | s | Power supply (VDD1) |
| 19 | D2 | in / out | Data bus, bit 2 (16 bit mode) |
| 20 | D1 | in / out | Data bus, bit 1 (16 bit mode) |
| 21 | D0 | in / out | Data bus, bit 0 (16 bit mode) |
| 22 | EX 8/16 | in | Data bus width select (8/16 bit) (Not Connected on PC Engine) |
| 23 | CK | in | Clock input |
| 24 | RESET | in | Reset input |
| 25 | VSYNC | in / out | Vertical Synchronization |
| 26 | HSYNC | in / out | Horizontal Synchronization |
| 27 | DISP | out | Screen blanking status (blanked/displayed) |
| 28 | SPBG | in / out | Pixel bus (sprite/background) (VD8) |
| 29 | VD7 | in / out | Pixel bus (palette value, bit 3) |
| 30 | VD6 | in / out | Pixel bus (palette value, bit 2) |
| 31 | VD5 | in / out | Pixel bus (palette value, bit 1) |
| 32 | +5V | s | Power Supply (VDD2) |
| 33 | GND | s | Power Supply (VSS2) |
| 34 | VD4 | in / out | Pixel bus (palette value, bit 0) |
| 35 | VD3 | in / out | Pixel bus (pixel value, bit 3) |
| 36 | VD2 | in / out | Pixel bus (pixel value, bit 2) |
| 37 | VD1 | in / out | Pixel bus (pixel value, bit 1) |
| 38 | VD0 | in / out | Pixel bus (pixel value, bit 0) |
| 39 | MWR | out | VRAM write strobe |
| 40 | MRD | out | VRAM read strobe |
| 41 | MD0 | in / out | VRAM data bus, bit 0 (VRAM chip 1) |
| 42 | MD1 | in / out | VRAM data bus, bit 1 (VRAM chip 1) |
| 43 | MD2 | in / out | VRAM data bus, bit 2 (VRAM chip 1) |
| 44 | MD3 | in / out | VRAM data bus, bit 3 (VRAM chip 1) |
| 45 | MD4 | in / out | VRAM data bus, bit 4 (VRAM chip 1) |
| 46 | MD5 | in / out | VRAM data bus, bit 5 (VRAM chip 1) |
| 47 | +5V | s | Power Supply (VDD3) |
| 48 | MD6 | in / out | VRAM data bus, bit 6 (VRAM chip 1) |
| 49 | MD7 | in / out | VRAM data bus, bit 7 (VRAM chip 1) |
| 50 | MD8 | in / out | VRAM data bus, bit 8 (bit 0 - VRAM chip 2) |
| 51 | MD9 | in / out | VRAM data bus, bit 9 (bit 1 - VRAM chip 2) |
| 52 | MD10 | in / out | VRAM data bus, bit 10 (bit 2 - VRAM chip 2) |
| 53 | MD11 | in / out | VRAM data bus, bit 11 (bit 3 - VRAM chip 2) |
| 54 | MD12 | in / out | VRAM data bus, bit 12 (bit 4 - VRAM chip 2) |
| 55 | GND | s | Ground (VSS3) |
| 56 | MD13 | in / out | VRAM data bus, bit 13 (bit 5 - VRAM chip 2) |
| 57 | MD14 | in / out | VRAM data bus, bit 14 (bit 6 - VRAM chip 2) |
| 58 | MD15 | in / out | VRAM data bus, bit 15 (bit 7 - VRAM chip 2) |
| 59 | MA0 | out | VRAM address bus, bit 0 |
| 60 | MA1 | out | VRAM address bus, bit 1 |
| 61 | MA2 | out | VRAM address bus, bit 2 |
| 62 | MA3 | out | VRAM address bus, bit 3 |
| 63 | MA4 | out | VRAM address bus, bit 4 |
| 64 | MA5 | out | VRAM address bus, bit 5 |
| 65 | MA6 | out | VRAM address bus, bit 6 |
| 66 | MA7 | out | VRAM address bus, bit 7 |
| 67 | MA8 | out | VRAM address bus, bit 8 |
| 68 | MA9 | out | VRAM address bus, bit 9 |
| 69 | MA10 | out | VRAM address bus, bit 10 |
| 70 | MA11 | out | VRAM address bus, bit 11 |
| 71 | GND | s | Ground (VSS4) |
| 72 | +5V | s | Power Supply (VDD4) |
| 73 | MA12 | out | VRAM address bus, bit 12 |
| 74 | MA13 | out | VRAM address bus, bit 13 |
| 75 | MA14 | out | VRAM address bus, bit 14 |
| 76 | MA15 | out | VRAM address bus, bit 15 |
| 77 | IRQ | out | IRQ output to HuC6280 IRQ1 input |
| 78 | BUSY | out | BUSY status output |
| 79 | A0 | in | Address bus, bit 0 |
| 80 | A1 | in | Address bus, bit 1 |
Clock input should be equal to the display pixel clock rate; e.g. 5.3693175 MHz.
The function of DISP, VSYNC and HSYNC is programmable.
The PCE uses MA15 as a chip-enable for the 64K of VRAM available in the PCE; access to addresses $8000-$FFFF means VRAM is disabled.
Other/External Documentation
*****************************************************************
* PC-Engine Video Display Controller Documentation *
* . . *
* ---+----------------------------------------------+--- *
* | MOST COMPLETE HuC6270 INTERNAL WORKINGS | *
* | DOCUMENT. IF YOU HAPPEN TO FIND *ANY* | *
* | WRONG INFORMATION, PLEASE CONTACT ME VIA | *
* | EMAIL AS SOON AS POSSIBLE SO I CAN FIX IT. | *
* ---+----------------------------------------------+--- *
* : : *
* *
* document revision 0.3 (3rd release) *
* *
* written by Emanuel Schleussinger in Feb 1998 *
* ( eschleus@luva.lb.bawue.de ) *
* Thanks to: *
* DAVID MICHEL for LOTS of information!!!!!!!!!! ;) *
* JENS CHR. RESTEMEIER for his EXCELLENT PCE-docu *
* DAVE SHADOFF for his emails and his TGSim source *
* NIMAI MALLE for his VDC explanations *
* VIDEOMAN for his excellent Hacking Web-Page *
* and some documents in there *
* PAUL CLIFFORD for an excellent HuC6270 register docu *
*****************************************************************
Revision reference:
-----+-----------------------------+---------------+----------
| rev 0.3:
| - improved the VDC register table A LOT thanks to the
| help of PAUL CLIFFORD. Thx for that cool doc, dude!
| (all those nasty 'unknown's are now eliminated)
| - more examples here and there.
| - fixed some docu bugs with help of David Michel.
| - Added Video Color Encoder reference.
| - Sprite storage description was WRONG, corrected now.
|
| rev 0.2:
| - Added Sprite information.
| - Fixed some major bugs in the docu.
| - Registers updated.
|
| rev 0.1 (initial release):
| - Still missing sprite docu, lots of undocumented registers.
-----+-----------------------------+---------------+----------
Document preface:
This document has been created for both beginners and advanced
programmers. There may be some information that you may well
consider 'unnecessary' (such as the introduction to planar image
storage), but please think of people who would really like to
program the PC-Engine, but dont have a clue on how some basic
techniques (like planar) work.
This document is in very early state and may well contain
a lot of information not being correct. For any wrong in-
formation in this document you may discover, please write
me a mail at eschleus@luva.lb.bawue.de so I can fix it and
release a new version.
The latest version of this document can always be obtained
at my homepage located at:
www.classicgaming.com/aec/
or just write me an email and ask me to send you the latest
revision.
Any help on improving this document is highly appreciated!
I think its the most complete one out there at this time.
Yours,
Manuel
eschleus@luva.lb.bawue.de
www.classicgaming.com/aec/
--------------------------------------------------------
----- T O P I C S -------------
--------------------------------------------------------
+-------------------------------------------+
| 1. Purpose of the VDC / General info |
| |
| 2. The VRAM structure / encoding VRAM data|
| |
| 3. Accessing the VDC from the CPU |
| |
| 4. The VDC registers in detail |
| |
| 5. The Sprites in the VRAM |
| |
| 6. The Sprite attribute table (SATB) |
| |
| 7. The Video Color Encoder |
| |
+-------------------------------------------+
--------------------------------------------------------
----- 1. Purpose of the VDC / General info -------------
--------------------------------------------------------
The VDC (Video Display Processor), also known as the HuC6270,
is the main graphics processing unit in the PC-Engine. Despite
the CPU of the PC-Engine is only 8-bit, the VDC is a full 16-bit
processor with very powerful capabilities. Its accessible from
the main system via 3 special opcodes that write/read data from/
into the Video Display. The VDC is connected to another chip known
as the HuC6260 VCE (Video Color Encoder), which supplies the color
palette data for the Video System.
The VDC in the PC-Engine has two modes of operation:
1. Background character processing
2. Sprite processing
The 64 kB VRAM that the VDC is connected to does NOT contain one big
bitmap with all the display information stored pixel by pixel like
on a Amiga or PC, the Graphics are stored tile-based. In case you do
not know what tile-based graphics are, be sure to read section 2
very carefully.
--------------------------------------------------------
----- 2. The VRAM structure / encoding VRAM data -------
--------------------------------------------------------
The VRAM of the PC-Engine is 64 kBytes in size. No chip other
than the VDC can access it. It contains all the important data
needed for the display generation.
The way graphical data is organized in the VRAM is called 'tile
based'. This means there is NOT a huge bitmap containing a color
index for every pixel, but only a list of pointers to small,
rectangular areas in the VRAM that will, aligned to each other,
make up the display. Explanation follows.
Think of it like this:
We have a 512*256 pixel 256 color screen. On a PC, for instance,
we would have to have the following VRAM structure:
+---------------------------------------+
| <--512 pixels across --> |
| |
| | 256
| | pixels
| | down
| |
| |
| |
| |
| |
+---------------------------------------+
The color depth is 8 bit ^= 256 colors
This would result in 512 * 256 * 8
= 1.048.576 bit
= 130 kbytes (roughly)
So, if the PC-Engine would do it the same way, it would not be
able to have such high resolutions due to the lack of VRAM.
Thats why data is stored in the VRAM as follows:
The screen background area is made up out of 8*8 pixels large
blocks, called the 'tiles', each tile having a color palette of
16 colors. There are 16 different palettes to choose from for
each tile, resulting in 256 different colors for the background
generation (the other 256 colors are reserved for sprite usage
which will be described later).
In the background, colour 0 of all palettes are equal. Colour 0 of
palette 0 determines colour 0 of all the background palettes. Even
though these colour CAN be set independently, the screen will not
reflect these settings.
-----Now, how are those tiles aligned to each other?
Starting at the very beginning of the VRAM ($0) there is the so-
called BAT (Block Attribute Table), which is a list of pointers
to tiles stored in the Video RAM. The amount of pointers varies
depending on how big the actual screen is. (As I told you, you
have 8*8 pixel tiles, so if the screen is larger, theres more
tiles). For our test screen (512*256), we would need:
512 / 8 = 64 tiles per line
256 / 8 = 32 tiles vertical
64 * 32 = 2048 tiles
That means, we would be in need of a BAT 2048 words in lenght.
-----WHY WORDS? How does a BAT pointer to the VRAM look like?
A Pointer to a tile in the VRAM must contain palette information
as well as the actual VRAM address where to find the tile. This
ONE WORD LONG index pointer looks like this:
PPPPAAAAAAAAAAAA
| |
| |
| +------- 12 lower bits: Index of the tile
|
+--------------- 4 upper bits: Palette number (0-15)
If you multiply the tile index by 32 (LSL #5 ;-), you will get
the actual VRAM pointer address.
The pointers in the BAT are ordered from the left to the right
and top to down.
----->Small example:<-----
Here is the first few words of data in the VRAM of HATRIS, just having
the intro screen up. If you look closely, note how VRAM was saved using
the same tiles over and over again in the BAT:
-----HOW CAN I SET THE SIZE OF THE BAT?
Easy, theres a VDC register dedicated to it, called the MWR register.
(find more about the MWR in SECTION 4)
MWR register mask:
xxxxxxxxxxHWWxxx (16 bits)
| |
| +--- width in tiles/pixels
| 00 = 32/256
| 01 = 64/512
| 10 = 128/1024
| 11 = 128/1024
|
+----- height in tiles/pixels
0 = 32/256
1 = 64/512
If you understood everything, you should now be asking:
"No TV can display a resolution of 1024 pixels across, so whats
this mode for?"
Answer: Check out the BXR and BYR registers used for SCROLLING ;)
(see SECTION 4)
-----HOW DOES THE TILE ITSELF LOOK LIKE IN THE VRAM?
Well, the tile itself is a piece of memory sized like this:
8 * 8 * 4 bits = 256 bits
| | |
| | +------- color index (4 bits per pixel)
| +----------- height in pixels
+--------------- width in pixels
On this issue, David Michel posted me a VERY good explanation on
how the data of a single tile is organized in the VRAM:
The PC-Engine use a planar mode rather than the well known chunky
mode of PCs, if you already have some experience decoding Atari ST
or Amiga gfx, you should easily understand the following.
In planar mode the 4 bits that form the color index are stored
in 4 separate bytes, let's say that we want to extract the color
index for the third pixel from the left :
color index
3rd pixel
+---+---+---+---+ +---+---+---+---+---+---+---+---+
| 3 | 2 | 1 | 0 | byte 1 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+ +---+---+---+---+---+---+---+---+
| | | | |
| | | +-----------------------+
| | |
| | | +---+---+---+---+---+---+---+---+
| | | byte 2 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | +---+---+---+---+---+---+---+---+
| | | |
| | +---------------------------+
| |
| | +---+---+---+---+---+---+---+---+
| | byte 3 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | +---+---+---+---+---+---+---+---+
| | |
| +-------------------------------+
|
| +---+---+---+---+---+---+---+---+
| byte 4 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| +---+---+---+---+---+---+---+---+
| |
+-----------------------------------+
It's as simple as that :)
The funny part is that those 4 bytes are not placed in order,
they are interleaved. Byte 1 & 2 are stored first, and bytes
2 & 3 are stored 16 bytes after, here is another nice drawing:
VRAM OFFSET
on pointer
(in bytes)
+---------------------+
0 | byte 1 & 2 of line 1|
+---------------------+
2 | byte 1 & 2 of line 2|
+---------------------+
4 | byte 1 & 2 of line 3|
+---------------------+
6 | byte 1 & 2 of line 4|
+---------------------+
8 | byte 1 & 2 of line 5|
+---------------------+
10 | byte 1 & 2 of line 6|
+---------------------+
12 | byte 1 & 2 of line 7|
+---------------------+
14 | byte 1 & 2 of line 8|
+---------------------+
+---------------------+
16 | byte 3 & 4 of line 1|
+---------------------+
18 | byte 3 & 4 of line 2|
+---------------------+
20 | byte 3 & 4 of line 3|
+---------------------+
22 | byte 3 & 4 of line 4|
+---------------------+
24 | byte 3 & 4 of line 5|
+---------------------+
26 | byte 3 & 4 of line 6|
+---------------------+
28 | byte 3 & 4 of line 7|
+---------------------+
30 | byte 3 & 4 of line 8|
+---------------------+
I think everyone should have got that right now. Thx David!
If you ask yourself what this was about, consider reading part
2 again. Part 3 won't be better ;-)
--------------------------------------------------------
----- 3. Accessing the VDC from the CPU ----------------
--------------------------------------------------------
---HOW CAN I TRANSFER DATA INTO THE VRAM?
Well, there are three memory locations involved that can be read/
written by the CPU to supply the VDC with data / read data from
the VDC (all in the I/O Memory Segment $FF):
Full address Access Purpose
$1FE000 R/W VDC Register select
$1FE002 R/W Low Data register
$1FE003 R/W High Data register
The first of the three locations here is the so-called REGISTER
SELECT. The VDC has 19 Registers (several of them being totally
unknown, btw) to access. To tell the VDC to which register you
want to write the value contained in $1FE002 (and $1FE003), simply
write the number of the register to write to into the low 5 bits
of $1FE000. As the VDC is a 16 bit processor (ALL VDC registers
are one word wide) in most cases you will need to supply both
of the data values.
Detailed description of the VDC ports by Videoman (slightly changed):
Address | Access | Description
(Mapped | mode |
to $FF) | |
--------------+--------+---------------------------------------------------
$0000 | R | 6270 Status register
| |
| | Different bits flag different conditions.
| | Not all are known.
| | (Note: can use special ST0 opcode to store
| | an immediate value.)
| | b 7 = 0
| | b 6 = 'BSY' flag
| | I believe this is '1' when a DMA transfer
| | is happening
| | b 5 = 'VD' flag
| | I believe this is a '1' when Vertical Sync
| | happens, otherwise a '0' (uncertain)
| | b 4 = 'DV' flag (unknown)
| | b 3 = 'DS' flag (unknown)
| | b 2 = 'RR' flag
| | Set during a Scanline interrupt (see RCR
| | register)otherwise '0'
| | b 1 = 'OR' flag (unknown)
| | b 0 = 'CR' flag (unknown)
| |
$0000 | W | 6270 Address register
| |
| | b 7-5 = ignored
| | b 4-0 = 6270 register number to access using
| | the 6270 data registers
| | ($0002 and $0003). Please see 6270
| | register list (SECTION 4) for details.
| |
$0002 | R/W | 6270 data LSB
| |
| | Note: can use special ST1 opcode to store
| | an immediate value.)
| |
$0003 | R/W | 6270 data MSB
| |
| | Note: can use special ST2 opcode to store
| | an immediate value.)
--------------+--------+---------------------------------------------------
----->One short example on this one:<------
To read the contents of Register 2 (VRAM-Read-Register) simply use the
following line of code:
ST0 #2
...and then the two data values will sort of 'mirror' the value in
this VDC register.
--------------------------------------------------------
----- 4. The VDC registers -----------------------------
--------------------------------------------------------
This huge and very complete list has been taken from Videomans
hardware map document, Jens' PCE documentation, and some information
to it was added by me.
REG ACCESS DESCRIPTION+
NO. MODE DETAILS
------------------------------------------------------------------------
0 R?/W MAWR - 'Memory Address Write Register'
b 15-0 this is the internal
register used as an address-counter when writing to VRAM.
All bits used (although no VRAM above $7FFF).
1 R?/W MARR - 'Memory Address Read Register'
b 15-0 this is the internal
register used as an address-counter when reading from VRAM.
All bits used (although no VRAM above $7FFF).
2 R VRR - 'VRAM Read Register'
b 15-0 this is the only valid read-access
from the data port. It reads the value from VRAM at the
address specified by the MARR. When the value is read
from the second byte-port at $0003, the MARR register
(ie. the 'address to read from') is auto-incremented
(although this may be a configurable behaviour).
All bits used.
2 W VWR - 'VRAM Write Register'
(write-access version of the above)
b 15-0 Write value to VRAM at the address specified by the MAWR.
When the value is written to the second byte-port at $0003,
the MAWR register (ie. the 'address to write to') is
auto-incremented (although this may be a configurable behaviour).
3 ? (unused) ?
4 ? (unused) ?
5 ? CR - 'Control Register'
b 15-13 unused
b 12-11 'IW' Address register auto-Increment
of the MAWR register
00 - normal increment (+1)
01 - +32
10 - +64
11 - +128
b 10 'DR' Dynamic RAM refresh (unknown by me though)
b 9-8 'TE' Selection of DISP terminal outputs
00 - DISP output "H" during display
01 - BURST colour burst inserting position is
indicated by output "L"
10 - INTHSYNC internal horizontal synchronous
signal
11 - not used
b 7 'BB' background (on/off) --+
1 - display background |
0 - no background > gets effective in
b 6 'SB' sprites (on/off) | next horizontal
1 - display sprites | display period.
0 - no sprites --+
b 5-4 'EX' (name unknown by me)
00 - vsync and hsync inputs
01 - vsync input, hsync output
10 - not used
11 - vsync and hsync outputs
b 3 irq (on/off)
0 = disabled
1 = enabled
b 2 rcr (on/off)
0 = disabled
1 = enabled
b 1 Enable interrupt for excess number detection of
sprites.
0 = disabled
1 = enabled
b 0 Enable interrupt for sprite collision detection.
0 = disabled
1 = enabled
Editor's note: bits 3-0 sound suspiciously like
interrupt-enable flags. Given what we know about
the interrupt vector table, is it logical to assume
that the remaining two IE bits stand for the
remaining two interrupt vectors? Then again, maybe not.
$FFFC-$FFFD NMI Vector
$FFFA-$FFFB TIMER Vector
$FFF8-$FFF9 IRQ1 Vector (for Video)
$FFF6-$FFF7 IRQ2 Vector (for BRK)
6 R RCR - 'Raster Counter Register'
b 15-10 ?
b 9-0 The rcr bit controls the generation of a raster
counter IRQ. The VDC generates an IRQ, when the
scanline specified in the RCR register is displayed.
You need to add 64 to the RCR register to get the
correct scanline.
7 R?/W BXR - 'Background X-Scroll Register'
b 15-10 (not used)
b 9-0 when the background map is a larger virtual
size than the viewing screen shows, this is
the viewing screen's x-offset (in pixels)
from the origin of the virtual background map.
8 R?/W BYR - 'Background Y-Scroll Register'
b 15-9 (not used)
b 8-0 when the background map is a larger virtual
size than the viewing screen shows, this is
the viewing screen's y-offset (in pixels)
from the origin of the virtual background map.
9 R?/W MWR - 'Memory-access Width Register'
Used to configure the size of the virtual background
map.
b 15-8 (not used)
b 7 'CM' (unknown - presumably 'Color Mode')
b 6-4 'SCREEN' These bits control virtual map size
as noted below.
b 6 virtual screen height
0 = 256 pixels / 32 tiles
1 = 512 pixels / 64 tiles
b 5-4 virtual screen width
00 = 256 pixels / 32 tiles
01 = 512 pixels / 64 tiles
10 = 1024 pixels / 128 tiles
11 = 1024 pixels / 128 tiles
Complete lookup of
available sizes in tiles:
-------------------------
000 - 32 x 32
001 - 64 x 32
010 - 128 x 32
011 - 128 x 32
100 - 32 x 64
101 - 64 x 64
111 - 128 x 64
b 3-2 Sprite pixel width
b 1-0 VRAM pixel width
10($A) ? HSR - 'Horizontal Sync Register'
b 15 (not used)
b 14-8 'HDS' Horizontal display start position -1.
b 7-5 (not used)
b 4-0 'HSW' Horizontal synchronous pulse width.
Mask = $7F1F
11($B) ? HDR - 'Horizontal Display Register'
b 15 (not used)
b 14-8 'HDE' Horizontal display ending period -1.
b 7 (not used)
b 6-0 'HDW' Horizontal display width in tiles -1.
Mask = $7F7F
added from Jens' PCE-documentation: Lower half of HDR:
It controls the horizontal width of display generation.
The value in this register is the number of horizontal
tiles minus one. Normal values are 31, for 32 tiles
and 256 pixel horizontally, 39, for 40 tiles or 320
pixel and 63, for 64 tiles or 512 pixel.
12($C) ? VPR - 'Vertical synchronous register'
b 15-8 'VDS' Vertical display start position -2.
b 7-5 (not used)
b 4-0 'VSW' Vertical synchronous pulse width.
Mask = $FF1F
13($D) ? VDW - 'Vertical display register'
b 15-9 (not used)
b 8-0 Vertical display width in pixels -1.
NOTE:
Unlike the HDR register, the information on the
vertical display width is split up in two registers,
this one storing the vertical width, and the next one
(VCR) containing the vertical display end position.
14($E) ? VCR - 'Vertical display END position register'
b 15-8 (not used)
b 7-0 Vertical display end position.
15($F) ? DCR - 'DMA Control Register'
The DCR, SOUR, DESR and LENR registers control
DMA operations.
The DMA operation starts, as soon as the length
is written into the LENR register
b 15-5 (not used)
b 4 - DSR DMA (VRAM-SATB transfer repetition)
b 3 - Increment (0)/decrement (1) of
destination address.
b 2 - Increment (0)/decrement (1) of
source address.
b 1 - Enable interrupt at completion of
VRAM-VRAM transfer.
Checked on completion of transfer.
b 0 - Enable interrupt at completion of
VRAM-SATB transfer.
Checked on completion of transfer.
16($10) R?/W SOUR - '(DMA) Source Address Register'
b 15-0 This register sets the source address
for DMA transfers.
All bits used (address pointer).
17($11) R?/W DESR - '(DMA) Destination Address Register'
b 15-0 This register sets the destination
address for DMA transfers.
All bits used
(although no VRAM above $7FFF).
18($12) R?/W LENR - '(DMA) Block Length Register'
b 15-0 This register sets the length of
the DMA transfer.
All bits used
(although no VRAM above $7FFF).
19($13) R?/W SATB - 'Sprite Attribute Table'
b 15-0 This register points to the start address
of the sprite attribute table.
All bits used
(although no VRAM above $7FFF).
--------------------------------------------------------
----- 5. The Sprites in the VRAM -----------------------
--------------------------------------------------------
Well, I will not try to explain what Sprites are here. Basically,
all of the PC-Engines' sprites are 16*16 to 32*64 pixels in size,
and have a sprite palette of 16 colors.
There are 16 separate sprite palettes available. (remember, there
was 16*16 colors for the background processing, those colors are
INDEPENDENT from the sprite palettes).
In the Sprites colours, colour 0 is transparent in all palettes,
although it does peek it's head in a peculiar place; beyond the display
width of the BG.
Explanation:
The background display area (in it's most often used setting) is 256x216.
The display width of a television may be adjusted to squash the screen
vertically, or horizontally. Even normal TVs show a little more that 256
TG-16 pixel wide, leaving a black border on the sides. This border colour is
actually controlled by sprite colour 0. The programmer can actually set the
screen width more narrow or vertically shorter, showing more of this area.
It's only use that I've ever implemented was in measuring the CPU load of
the TG-16 during development.
--HOW ARE SPRITES STORED IN THE VRAM?
For the sprite characters the principe is the same as for the background
tiles, but in place of using bytes (8 pixels) they use words (16 pixels).
Note that the words still use the same encoding as all word data within the
PC-Engine, this means that the first byte of the word is the lower byte.
Sprite data is stored like in the following drawing:
Byte Data
offset
+-------------------+
0 | plane 1 of line 1 |
+-------------------+
2 | plane 1 of line 2 |
+-------------------+
. .
: :
30 | plane 1 of line 16|
+-------------------|
32 | plane 2 of line 1 |
+-------------------+
34 | plane 2 of line 2 |
+-------------------+
36 | plane 2 of line 3 |
+-------------------+
. .
: :
46 | plane 2 of line 16|
+-------------------+
48 | plane 3 of line 1 |
......and so on.
Not only you can display sprites, you can do some sort of funny stuff
with them, like mirroring, for instance. All this is controlled in the
so-called SPRITE ATTRIBUTE TABLE.
--------------------------------------------------------
----- 6. The Sprite attribute table (SATB) -------------
--------------------------------------------------------
The sprites' positions and attributes are defined in the so-
called SPRITE ATTRIBUTE TABLE (SATB). The SATB can be contained any-
where in the VRAM ($0000-$7FFF).
--HOW DOES THE VDC KNOW WHERE THE SATB IS TO BE FOUND?
The VDC has a special register containing nothing but the start
address of the SATB in the VRAM. This is register 19 (SEE SECTION 4)
The actual sprite attributes are stored at the address mentioned
above. For aech sprite, there is a 4 word long attribute section,
which looks as follows:
Word | Access | Description
offset | mode |
--------------------------------------------------------------------------
0 R/W Y position
b 15-10 (unused)
b 9-0 y position (relative to
virtual-screen origin)
1 R/W X position
b 15-19 (unused?)
b 9-0 x position (relative to
virtual-screen origin)
2 R/W Pattern address
b 15-11 (unused?)
b 10-0 sprite data VRAM address shifted
right 5 bits(Shift left 6 bits to
get real VRAM address)
3 R/W Sprite attributes
b 15 y-invert flag (upside-down)
b 14 unused
b 13-12 'CGY'
00 = sprite is 1 'cell' (16 pixels) high
01 = sprite is 2 cells high (32 pixels)
10 = invalid
11 = sprite is 4 cells high (64 pixels)
b 11 x-invert flag (left-right invert)
b 10-9 unused
b 8 'CGX'
0 = sprite is 1 'cell' wide (16 pixels)
1 = sprite is 2 cells wide (32 pixels)
b 7 'SPBG'; is sprite in foreground (in front
of CG) or background (behind CG)
b 6-4 unused
b 3-0 sprite colour (i.e. which of 16 sprite
palettes to use)
Patents
Patent for Displaying Sprites
Note: terminals with a High value are a binary 1 and Low is a binary 0.
United States Patent Number: 4951038APPARATUS FOR DISPLAYING A SPRITE ON A SCREEN
|
In [Figure 1], there is shown an apparatus for displaying an image on a screen which is mainly composed of a Video Display Controller (1), a CPU (2), a Video Color Encoder (3), and a Programmable Sound Generator (4). The Video Display Controller (1) supplies the Video Color Encoder (3) with image data for a story which are read from a VRAM (7) under the control of the CPU (2) reading a program stored in a ROM (5). The CPU (2) controls a RAM (6) to store data, calculation or arithmetical results etc. temporarily in accordance with a program stored in the ROM (5). The Video Color Encoder (3) is supplied with image data to produce RGB analog signals or video color signals including luminance signals and color difference signals to which the RGB signals are matrix-converted by using color data stored therein. The Programmable Sound Generator (4) is controlled by the CPU (2) reading a program stored in the ROM (5) to produce audio signals making left and right stereo sounds. The video color signals produced at the Video Color Encoder (3) are of composite signals supplied through an interface (8) to a video display (9), while the RGB analog signals are directly supplied to video display (9) which is used as an exclusive monitor apparatus. The left and right analog signals supplied from the Programmable Sound Generator (4) are amplified at amplifiers 11a and 11b to make sounds at speakers 12a and 12b. |
|
|
In [Figure 2A], there is shown the Video Display Controller (1) transferring data between the CPU (2) and VRAM (7) which comprises a control unit 20 including various kinds of registers to be described later, an address unit (21), a CPU read/write buffer (22), and sprite shift register (24), a background shift register (25), a data bus buffer (26), a synchronic circuit (27), and a priority circuit (28). The control unit (20) is provided with a BUSY terminal being Low to keep the CPU (2) writing data into the VRAM (7) or reading data therefrom in a case where the Video Display Controller (1) is not in time for the writing or reading of the date, an IRQ terminal supplying an interruption request signal, a CK terminal receiving a clock signal of a frequency for one pixel (one picture element), a RESET terminal receiving a reset signal for initializing the Video Display Controller (1), and an EX 8/16 terminal receiving a data bus width signal for selecting one of 8 and 16 bit data buses. The address unit (21) is connected to terminals MA0 to MA15 supplying address signals for the VRAM (7) which has, for instance, a special address region of 65,536 words. The address unit (21), CPU read/write buffer (22), Sprite Attribute Table (23), sprite shift register (24), and background shift register (25) are connected to terminals MD0 to MD15 through which data are transferred to and from the VRAM (7). The Sprite Attribute Table buffer (23) is a memory for storing X and Y display positions, pattern codes and control data of sprites each composed of 16×16 pixels as described in more detail later. The sprite shift register (24) stores pattern and color data of a sprite read from a Sprite Generator in the VRAM (7) which is accessed in accordance with the pattern codes stored in the Sprite Attribute Table (23) as described in more detail later. The background shift register (25) stores pattern data, along with CG color, read from a character generator in the VRAM (7) in accordance with an address based on a character code of a Background Attribute Table in the VRAM (7) which is accessed in an address decided by a raster position as also described in more detail later. The data bus buffer (26) is connected to terminals D0 to D15 through which data are supplied and received. In the Video Display Controller (1), 8 or 16 bit interface is selected to comply with a data width of a system including the CPU (2) wherein the terminals D0 to D7 among the terminals D0 to D15 are occupied when the 8 bit interface is selected. The synchronic circuit (27) is connected to a DISP terminal indicating a display period, a VSYNC terminal from which a vertical synchronous signal for a video display (9) is supplied and in which an external vertical synchronous signal is received, and a HSYNC terminal from which a horizontal synchronous signal for a video display (9) is supplied and in which an external horizontal synchronous signal is received. The priority circuit (28) is connected to terminals VD0 to VD7 through which video signals are supplied, and a SP/BG (VD8) terminal being High when the video signals are of a sprite and being Low when the video signals are of a background. The aforementioned control unit 20 is also connected to a CS terminal being Low wherein the CPU (2) is able to read data from registers therein and sprite data thereinto, a RD terminal receiving a clock signal for the reading thereof, a WR terminal receiving a clock signal for the writing thereof, and terminals A0 and A1 which are connected to address bus of the CPU (2). Further, the Video Display Controller (1) is provided with a MRD terminal being Low when the CPU (2) reads data from the VRAM (7), and a MWR terminal being Low when the CPU (2) writes data into the VRAM (7). |
|
|
In [Figure 2B], there is shown an apparatus for displaying a sprite on a screen in an embodiment according to the invention wherein the reference numerals 31 and 32 indicate a Sprite Attribute Table and Sprite Generator in the VRAM (7) respectively. The Sprite Attribute Table (31) can include, for instance, 64 sprites, while the Sprite Generator (32) can include, for instance, one thousand and twenty-four sprites. In the Sprite Attribute Table (31), addresses of 0 to 63 are assigned to the 64 sprites to give a priority thereto in the order of the address 0>1> >62>63. Each of the sprites is composed of 16×16 bits, and includes X and Y coordinates, pattern codes and control data. As to each of the sprites, the Y coordinate is compared with a raster signal supplied from a scanning raster producing circuit 33 in a coincidence detection circuit (34) whereby sprites each having a Y coordinate coincident with a raster signal are stored into a pattern code buffer (35) which can store a maximum number of 16 sprites by referring to a corresponding one of the addresses 0 to 63. A selector (36) selects a pattern code of the Sprite Attribute Table (31) in accordance with an address stored in the pattern code buffer (35) to access the Sprite Generator (32) in regard to an address which is of a selected pattern code, thereby reading pattern data from the Sprite Generator (32). The pattern data thus obtained are stored into a pattern data buffer (37) along with an X coordinate corresponding thereto read from the Sprite Attribute Table (31). The storing of sprites into the pattern code buffer (35) is performed at a horizontal display period preceding to the present horizontal display period by one scanning raster, while the storing of pattern data into the pattern data buffer (37) is performed at a following horizontal retrace period. When a scanning raster at which pattern data are displayed has come, the X coordinate thus stored in the pattern data buffer (37) is compared with a counted value of a horizontal pixel clock counter (PCC) (38) in a coincidence detection circuit (39) whereby pattern data having an X coordinate coincident with the counted value are supplied to a parallel/serial converting circuit (40). In the parallel/serial converting circuit (40), parallel pattern data are converted into serial pattern data which are supplied through a gate circuit (42) to a video display (9). The gate circuit (42) is controlled to be turned on and off in accordance with a content of a starting coordinates registration circuit (43) by the CPU (2). The content thereof is X and Y coordinates by which the starting coordinates of a display region is defined on a display screen. |
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| In [Figures 3A to 3U], there are shown various kinds of registers included in the Control Unit (20) of the Video Display Controller (1). (a) Address Register ([Figure 3A]) A register number AR is exclusive written into the address register designating one of the memory address write register to DMA VRAM-SATB source address register as shown in [Figures 3C to 3U] so that data are writing into the Video Display Controller (1) under the condition that the A1 and CS terminals thereof are Low. In a case where 16 bit data bus is selected, the EX 8/16 terminal is 0, the A1 terminal is 0, the R/W terminal is W, and the A0 terminal is no matter. In a case where 8 bit data bus is selected, the EX 8/16 terminal is 1, the A0 and A1 terminals are 0, and the R/W terminal is W. | |
| (b) Status Register ([Figure 3B]) A bit corresponding to one of interruption jobs is set to be High in the status register to make the interruption active when a cause of the interruption which is enabled by an interruption permission bit of a Control Register and DMA Control Register as showing in [Figures 3G and 3Q] is occurred. When the status is read from the status register, the corresponding bit is cleared automatically. The status indicating bits are as follows. (1) bit 0 (CR) - collision of sprites It is indicated that the sprite number 0 of a sprite is collided with any one of the sprite numbers 1 to 63 of sprites. (2) bit 1 (OR) - more sprites than a predetermined number (2.1) a case where more than 17 sprites are detected on a single raster line. (2.2) a case where data of a sprites which is designated are not transferred to a data buffer in a horizontal trance period. (2.3) a case where a bit of CGX in control data of a sprite by which two sprites are joined in a horizontal direction is set so that data of the sprites are not transferred to a data buffer. (3) bit 2 (PR) - detection of raster It is indicated that a value of a raster counter becomes a predetermined value of a raster detecting register. (4) bit 4 (DS) - finishing of DMA transfer It is indicated that data transfer between the VRAM (7) and Sprite Attribute Table buffer (23) is finished. (5) bit 4 (DV) - finishing of DMA transfer It is indicated between two regions of VRAM (7) is finished. (6) bit 5 (VD) - vertical retrace period It is indicated that the VRAM (7) accessed for the writing or reading of data by the CPU (2) so that the BUSY terminals is 0. | |
| (c) Memory Address Write Register (register name 0x00, [Figure 3C]) A starting address MAWR is written into the memory address write register so that the writing of data begins at the starting address of the VRAM (7). | |
| (d) Memory Address Read Register (register number 0x01, [Figure 3D]) A starting address MARR is written into the memory address read register. When the upper byte of the starting address is written thereinto, data are begun to be read from the starting address of the VRAM (7) so that data thus read are written into a VRAM data read register as showing in [Figure 3F]. There after, the starting address MARR is automatically incremented by one. | |
| (e) VRAM Data Write Register (register number 0x02, [Figure 3E]) Data which are transferred from the CPU (2) to the VRAM (7) are written into the VRAM data write register. When the upper byte of the data VWR is written thereinto, the Video Display Controller (1) begins to write the data into the VRAM (7) and the address MAWR of the memory address write register is automatically incremented by one upon writing of the data. | |
| (f) VRAM Data Read Register (register number 0x02, [Figure 3F]) Data which are transferred from the VRAM (7) to the CPU (2) are written into the VRAM data read register. When the upper byte of the data VRR is read therefrom, the reading of data is performed at the following address of the VRAM (7). | |
(g) Control Register (register number 0x05, [Figure 3G])
An operating mode of the Video Display Controller (1) is controlled in accordance with the
following bits of the Control Register.
(1) bits 0 to 3 (IE) - enable of interruption request
(1.1) bit 0 - collision detection of sprites
(1.2) bit 1 - excess number detection of sprites
(1.3) bit 2 - raster detection
(1.4) bit 3 - detection of vertical retrace period
(2) bits 4 and 5 (EX) - external synchronization
(3) bit 6 (SB) - sprite blanking
It is decided whether a sprite should be displayed on a screen or not.
The control of the bit is effective in the following Horizontal Display Period.
(3.1) 0 - blanking of a sprite
(3.2) 1 - display of a sprite
(4) bit 7 (BB) - background blanking
It is decided whether background should be displayed on a screen or not.
The control of the bit is effective in the following Horizontal Display Period.
(4.1) 0 - blanking of background
(4.2) 1 - display of background.
(3.4) As a result, when bits 6 and 7 are both 0, there is a resulted "burst mode" in
which the following operations can be performed.
(3.4.1) The access to the VRAM (7) is not performed for a display, but the VRAM (7) is
accessed by the CPU (2).
(3.4.2) DMA between two regions of the VRAM (7) is possible to be performed at any
time.
In such occasions, the terminals VD0 and VD7 are all Low while the SP/BG terminal is
High. On the other hand, when the bits 6 and 7 are both 1, there is released from
the "burst mode".
(5) bits 8 and 9 (TE) - selection of DISP terminal outputs
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| (h) Raster Detecting Register (register number 0x06, [Figure 3H]) A raster number RCR at which an interruption job is performed is written into the raster detecting register. An interruption signal is produced when a value of a raster counter is equal to the raster number RCR. The raster counter is preset to be 64 at a preceding scanning raster line to a display starting raster line as described in more detail later, and is increased at each raster line by one. | |
| (i) BGX Scroll Register (register number 0x07, [Figure 3I]) The BGX scroll register is used for a horizontal scroll of background on a screen. When a content BXR is rewritten therein, the content is effective in the following raster line. | |
| (j) BGY Scroll Register (register number 0x08, [Figure 3J]) The BGY scroll register is used for a vertical scroll of background on a screen. When a content BYR is rewritten therein, the content is effective to be as "BYR + 1" in the following raster line. | |
(k) Memory Width Register (register number 0x09, [Figure 3K])
(1) bits 0 and 1 (VM) - VRAM pixel width
A pixel width in which an access to the Background Attribute Table and character
generator, DMA and access of the CPU (2) to the VRAM (7) during a horizontal display
period are performed is written into the bits of the memory width register. The pixel
width is decided dependent on a memory speed of the VRAM (7). When the bits 0 and 1
are re-written therein, the content is effective at the beginning of a vertical
retrace period.
BAT is for Background Attribute Table, and CG is for character generator.
(2) bits 2 and 3 (SM) - sprite pixel width
A pixel width which an access to the sprite generator is performed during a horizontal
retrace period is written into the bits of the memory width register.
(3) bits 4 to 6 (SCREEN)
The number of character in X and Y directions of a fictitious screen is decided
dependent on the content of the bits. When a content is effective at the beginning
of a vertical retrace period.
(4) bit 4 (CM) - CG mode When a VRAM pixel width is of 4 pixels, a color block of a character generator is changed dependent on the bit. A content is writtent into the bit, the content is effective in the following raster line. |
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| (l) Horizontal Synchronous Register (register number 0x0A, [Figure 3L]) (1) bits 1 to 4 (HSW) - horizontal synchronous pulse A pulse width of Low level of a horizontal synchronous pulse is set as an unit of a character cycle. One of 1 to 32 is selected by using 5 bits to comply with the specification of a video display. (2) bits 8 to 14 (HDS) - starting position of horizontal display A period between a rising edge of a character cycle. An optimum position in a horizontal direction on a video display is decided by a content of the 7 bits. When it is assumed that a horizontal display position (horizontal back porch) is N, N - 1 is written into HDS bits. | |
| (m) Horizontal Display Register (register number 0x0B, [Figure 3M]) (1) bits 0 to 6 (HDW) - horizontal display width A display period in each raster line is set as an unit of a character cycle, and is decided in accordance with the number of characters in the horizontal direction on a video display dependent on a content of the 7 bits. If it is assumed that a horizontal display position is N, N - 1 is written into HDW bits. (2) bits 8 to 11 (HDE) - horizontal display ending position A period between an ending of a Horizontal Display Period and a rising edge of a horizontal synchronous signal is set as an unit of a character cycle. An optimum position of a horizontal display is set on a video display by the 7 bits. When it is assumed that a horizontal display ending position (horizontal back porch) is N, N -1 is written into HDE bits. | |
| (n) Vertical Synchronous Register (register number 0x0C, [Figure 3N]) (1) bits 0 to 4 (VSW) - vertical synchronous pulse width A pulse width of a vertical synchronous signal is decided in a width of Low level as a unit of a raster line. One of 1 to 32 is selected to comply with a specification of a video display. (2) bits 8 to 15 (VDS) - vertical display starting position A period between a rising edge of a vertical synchronous signal and a vertical synchronous starting position is set as an unit of a raster line. When it is assumed that a vertical display starting position (vertical back porch) is N, N-2 is written into the bits. | |
| (o) Vertical Display Register (register number 0x0D, [Figure 3O]) A vertical display period (display region) is set as an unit of a raster line. A vertical display width is decided in accordance with the number of raster lines to be displayed on a video display which is defined by a content of the 9 bits. When it is assumed that a vertical display width is N, N - 1 is written into the VDW bits. | |
| (p) Vertical Display Ending Position Register (register number 0x0E, [Figure 3P]) A period between a vertical display ending position and a rising edge of a vertical synchronous signal is set as an unit of a raster line. When it is assumed that a vertical optimum position (vertical front porch) is N to be defined by the 8 bits, N is written into the VCR bits. | |
| (q) DMA Control Register (register number 0x0F, [Figure 3Q]) (1) bit 0 (DSC) - Enable an interruption at the finishing of transfer between the VRAM (7) and Sprite Attribute Table buffer (23). It is decided whether or not an interruption is enabled at the finishing time of the transfer. (1.1) 0 - disable (1.2) 1 - enabled (2) bit 1 (DVC) - Enable an interruption at the finishing of transfer between two regions of the VRAM (7). It is decided whether or not an interruption is enabled finishing time of the transfer. (2.1) 0 - disable (2.2) 1 - enabled (3) bit 2 (SI/D) - Increment/decrement of a source address One of automatically increment and decrement of a source address is selected in a transfer between two regions of VRAM (7). (3.1) 0 - increment (3.2) 1 - decrement (4) bit 3 (DI/D) - Increment/decrement of a destination address One of automatically increment and decrement of a destination address is selected in a transfer between two regions of VRAM (7). (4.1) 0 - increment (4.2) 1 - decrement (5) bit 4 (DSR) - repetition of a transfer between the VRAM (7) and the Sprite Attribute Table buffer (23) is enabled. (5.1) 0 - disable (5.2) 1 - enabled | |
| (r) DMA Source Address Register (register number 0x10, [Figure 3R]) A starting address of a source address is allocated in a transfer between two regions of the VRAM (7). | |
| (s) DMA Destination Address Register (register number 0x11, [Figure 3S]) A starting address of a destination address is allocated in a transfer between two regions of the VRAM (7). | |
| (t) DMA Block Length Register (register number 0x12, [Figure 3T]) A length of a block is defined in a transfer between two regions of the VRAM (7). | |
| (u) DMA VRAM-SATB Source Address Register (register number 0x13, [Figure 3U]) A starting address of a source address is allocated in a transfer between the VRAM (7) and Sprite Attribute Table buffer (23). | |
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In [Figure 4A], there is shown an address in a Background Attribute Table for a character on a fictitious screen. A character and color to be displayed at each character position are stored in the Background Attribute Table. A predetermined number of Background Attribute Tables are stored in a region the first address of which is 0 in the VRAM (7). The fictitious screen shown therein which is one example is of 32×32 characters. |
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In [Figure 4B], there is shown a screen which is framed by writing respective predetermined values into the aforementioned Horizontal Synchronous Register, Horizontal Display Register, vertical synchronous register and Vertical Display Register as shown in [Figures 3L, 3M, 3N and 30]. Although the respective predetermined values for the registers are not explained here, a display region is defined in accordance with HDW + 1 in the Horizontal Display Register and VDW + 1 in the Vertical Display Register. In the embodiment, the starting coordinates (x,y) for the display region is indicated to be as (32, 64). |
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In [Figures 5A and 5B], there are shown Background Attribute Tables (BATs) in the VRAM (7) each of 16 bits to have a character code of lower 12 bits for designating a pattern number of a character and a CG color of upper 4 bits for designating a CG color code. |
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In [Figures 6A and 6B], there are shown Sprite Attribute Tables (SATs) (31) in the VRAM along with a Sprite Generator (32). Each of the Sprite Attribute Tables (31) is composed of 16 × 4 bits, that is, four words to define a sprite. Therefore, 64 sprites are defined by 256 words. In the Sprite Attribute Table, lower 10 bits in the first word designate a horizontal position (0 to 1023) of a sprite. For this purpose, one of 0 to 1023 is written into an X coordinate therein. In the same manner, lower 10 bits in the second word designate a vertical position (0 to 1023) of a sprite, and one of 0 to 1023 is written into a Y coordinate therein. On the other hand, lower 11 bits in the third word is for a pattern number which is an address for a Sprite Generator (32), while the fourth word is for control bits including Y (X15), CGY (2 bits of X13 and X12), X (X11), CGX (X8), SP/BG (X7) and a color for a sprite (4 bits of X3 to X0) in the direction of MSB to LSB.
The control bits are defined as follows.
(1) setting of Y
A sprite is displayed to be reversed in the Y direction.
(2) setting of CGX
Two sprites consisting of a sprite to be addressed in the Sprite Generator (32) and the other
sprite of the following address are displayed to be joined in the horizontal direction
(3) setting of X
A sprite is displayed to be reversed in the X direction.
(4) setting of CGY
The 2 bits X13 and X12 define three modes to be described in more detail later.
(5) SP/BG The bit X7 designates a priority between displayed of background and sprite (5.1) 0 - background (5.2) 1 - sprite (6) sprite color The bits X3 to X0 into an area color of a sprite. Each sprite has four facets to be called SG0 to SG3 each being of 16x16 pixels so that one sprite occupies 64 words. The writing of data into a Sprite Attribute Table (31) is performed such that the data are not transferred from the CPU (2) directly to the VRAM (7), but in DMA transfer from the CPU (2) to the Sprite Attribute Table buffer (23). In operation, a sprite SP having standard coordinates (2,2) is displayed on a video display (9) having 1024 display pixels respectively in the X and Y directions as shown in [Figure 7]. In displaying the sprite SP thereon, the Y coordinates of the 64 Sprite Attribute Tables (31) are compared in turn with a raster signal supplied from the scanning raster signal producing circuit (33) at the coincidence detection circuit (34) to pick up sprites each having a Y coordinate 2 which is then stored in its stripe number among the stripe numbers 0 to 63 into the pattern code buffer (35) when a horizontal display period of a scanning raster number 1 is started in the apparatus as shown in [Figure 2B]. In this occasion, 16 sprites can be stored in the pattern code buffer (35) at the maximum. During a horizontal retrace period before which a scanning raster number 1 is finished and after which a scanning raster number 2 is started, address signals are produced in the selector (36) in accordance with the sprite numbers stored in the pattern code buffer (35) and pattern codes in the Sprite Attribute Tables (31) so that pattern data are read from the Sprite Generator (32) in accordance with the address signals thus produced. The pattern data are stored in the pattern data buffer (37) along with X coordinates corresponding thereto in the Sprite Attribute Tables (31). When a horizontal display period of the scanning raster number 2 is started, the X coordinates stored in the pattern data buffer (37) are compared with counted values of the horizontal pixel clock counter (38) at the coincidence detection circuit (39). In the comparison, pattern data for the sprite SP are read to be supplied to the parallel/serial converting circuit (40) from the pattern data buffer (37) when the counted value corresponds to x=2. The parallel pattern data are converted into serial pattern data in the parallel/serial converting circuit (40) so that a picture element (2, 2) of the sprite SP is displayed on the video display (9) in accordance with the serial pattern data passed through the gate circuit (42). Thereafter, 15 picture elements (3, 2), (4, 2) - (17, 2) are displayed thereon to complete the display of the sprite SP on the y=2 raster line. As a matter of course, control data of the Sprite Attribute Table (31) corresponding to the sprite SP are used to control the display thereof. In moving the sprite SP having the standard coordinates (2, 2) to a display position having a standard coordinates (X, Y) to be a sprite SP', the X and Y coordinates (2, 2) of the Sprite Attribute Table (31) corresponding to the sprite SP are only changed to be X and Y coordinates (x, y) without changing contents of the Sprite Generator (32) and necessitating the re definition of a pattern. The sprites SP and SP' are displayed in accordance with the combination of more than one facets among the four facets SG0 to SG3. Such a combination of facets SG0 to SG3 is shown in [Figure 8]. For instance, all of the four facets SG0 to SG3 are combined to display a sprite SP1, while the facets SG0 and SG1 are combined to display a sprite SP2. As clearly understood from the example, 24 display patterns are obtained in accordance with the calculation 4 × 3 × 2 = 24 so that a desired pattern can be selected from the 24 patterns in accordance with control data in a Sprite Attribute Table. The four facets SG0 to SG3 are of different colors each to be designated by an area color code. Next, the aforementioned CGX and CGY defined by control data in a Sprite Attribute Table (31) are explained. |
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In [Figure 9], there is shown a Sprite Generator (SG) (32) comprising pattern data A, B, C--. In accordance with the definition of CGX and CGY as explained before, various kinds of sprite patterns each having a different color and size from others are obtained without increasing a memorizing area of the Sprite Generator (32) as shown in [Figures 10A to 10E]. Further, X, Y, CGX and CGY are explained more in conjunction with [Figures 11A to 11C and 12A to 12C]. |
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In [Figure 11A], when a bit X in a Sprite Attribute Table (31) is set to be 1, a sprite is displayed to be reversed in a left-side right manner. On the other hand, when a bit Y in the Sprite Attribute Table (31) is set to be 1, the sprite is displayed to be reversed in an upside down manner. As a matter of course, when the bits X and Y are set to be 1, the sprite is displayed to be reversed in a left-side right and upside down manner. |
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In [Figures 11B and 11C], a CGX control mode as explained before is again explained. When a CGX bit is set to be 1, a sprite of an address designated by a pattern code in a Sprite Attribute Table and a sprite of a preceding or following address to the designated address are displayed to be joined in the X direction. To be more concrete, if the designated address is 00001000110 as shown in [Figure 11B], a sprite of an address 00001000100 in which the bit X' is changed from 1 to 0 is positioned to the left, and a sprite of the designated address in which the bit X1 is 1 is positioned to the right so that a sprite of the CGX mode is obtained as shown in [Figure 11C] wherein two patterns of X = 0 and Y = 0 and X = 1 and Y = 0 are displayed. |
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In [Figures 11B and 11C], a CGX control mode as explained before is again explained. When a CGX bit is set to be 1, a sprite of an address designated by a pattern code in a Sprite Attribute Table and a sprite of a preceding or following address to the designated address are displayed to be joined in the X direction. To be more concrete, if the designated address is 00001000110 as shown in [Figure 11B], a sprite of an address 00001000100 in which the bit X' is changed from 1 to 0 is positioned to the left, and a sprite of the designated address in which the bit X1 is 1 is positioned to the right so that a sprite of the CGX mode is obtained as shown in [Figure 11C] wherein two patterns of X = 0 and Y = 0, and X = 1 and Y = 0 are displayed. In [Figures 12A to 12C], a CGY display mode as briefly explained before is again explained. In the CGY display mode, 2 bits X3 and X2 of a pattern code in a Sprite Attribute Table are controlled so as to be (0, 0), (0, 1), (1, 0) and (1, 1). Therefore, if it is assumed that a pattern code in a Sprite Attribute Table is 00001000110, an address map of a Sprite Generator is illustrated as shown in [Figure 12A]. As a result, a sprite is displayed in 4CGY mode as shown in [Figure 12B] wherein X and Y bits are not set to be 1 and in [Figure 2C] wherein X bit is not set to be 1, while Y bit is set to be 1. As clearly understood from the CGX and CGY display modes, a pattern size of a sprite is of 2×16×16 pixels in the CGX mode, and that of a sprite is of 4×16×16 pixels in the 4CGY mode so that the starting coordinates (x,y) of the display region are set to be (32, 64) in the embodiment. For the reason, the starting coordinates may be changed dependent on CGX and CGY modes. Referring back to [Figure 2B], the starting coordinates (x,y) of the display region defined by (HDW + 1) × (VDW + 1) as explained in [Figure 4B] is set in the start coordinates registration circuit (43) to be (32, 64). During the horizontal display period of a raster number 1, a counted value of the horizontal pixel clock counter (38) and an X coordinate of the pattern data buffer (37) are compared with each other. In this comparison, pattern data having an X coordinate equal to the counted value are read from the pattern data buffer (37) to be converted from parallel to serial in the parallel/serial converting circuit (40). In this occasion, all of Y coordinates of the sprites are 1, while each of X coordinates of the sprites ranges from X to X + 15, where X is a counted value of the horizontal pixel clock counter (38) because each sprite is of 16 × 16 pixels. Therefore, when the CGX display mode is performed, that ranges from X to X + 31. Due to the fact that the Y coordinates are all 1, the serial pattern data can not be passed through the gate circuit (42) which is controlled in accordance with the starting coordinates (32, 64) of the start coordinates registration circuit (43) by the CPU (2) regardless of X coordinates thereof so that the pattern data are not displayed on the video display (9). In this manner, the control of passing serial pattern data through the gate circuit (42) is performed in regard to a raster number 2, 3--k--by the CPU (2). Thus, serial pattern data having a horizontal display position larger than 32 and vertical display position larger than 64 are passed through the gate circuit (42) to be displayed on the video display (9). As a result, the blanking of a sprite can be performed so that a sprite is appeared smoothly from the top, bottom, left and right onto the video display (9), and disappeared in the same manner. In the control of displaying a sprite, the number of sprites to be designated in the coincidence detection circuit (34) is checked by the CPU (2). When the CPU (2) detects the number to be more than a predetermined number, 16 in the embodiment, a warning signal is produced therefrom to indicate the occurrence on the video display (9). In other words, the seventeenth sprite which is designated to be displayed is not displayed on the video display (9). In a case where all of pattern data for sprites to be designated are not transferred from the Sprite Generator (32) to the pattern data buffer (37) in a horizontal retrace period, it is understood in the CPU (2) that pattern data exceed a limitation of a display on the video display (9). Such an excess pattern data are liable to be read from the Sprite Generator (32), for instance, in a case of CGX display mode as explained before. Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to thus limited but are to be construed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth. |
Patent for Multiple Screen Windows
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In [Figure 8], there is shown an apparatus for controlling the access of VRAM (7) in a first embodiment according to the invention. The apparatus comprises a CPU (2), a raster setting register (50), a circuit (33) for producing scanning raster signals, a comparison circuit (51) including a raster counter (not shown) which counts the scanning raster signals for comparing the counted value N of the raster counter with a raster number (RN) of the raster setting register (50), and a display screen (9) which is controlled to display a background and a sprite by the CPU (2). The raster number (RN) is defined by 8 bits of 0 to 7 so that one of the raster number 0 to 255 (28 = 256) can be set therein. In operation, the raster number (RN) of the raster setting register (50) is set to be n: as shown in [Figure 9A] by the CPU (2). The raster counter of the comparison circuit (51) counts the scanning raster signals supplied from the circuit (33). When the counted value N is equal to and larger than 0, and less than the set value n:(0 ≦ N < n1), the set value n1 is held therein. When the counted value N is equal to the set value n1, the comparison circuit (51) supplies a coincidence signal to the CPU (2) so that the raster number (RN) of the raster setting register (50) is then set to be n2 by the CPU (2) as shown in [Figure 9B]. When the counted value N is equal to and larger than n1, and less than the set value n2 (n1 < N ≦ n2), the set value n2 is held therein. When the counted value N is equal to the set value n2 is held therein. When the counted value N is equal to the set value n2, a second coincidence signal is supplied from the comparison circuit (51) to the CPU (2) so that the raster number (RN) of the raster setting register (50) is set to be n3 by the CPU (2) as shown in [Figure 9C]. In the same manner, a third coincidence signal is supplied from the coincidence circuit (51) when the counted value N is equal to the setting value n3. Upon receiving the first to third coincidence signals, the CPU (2) divides the display screen (9) into four regions in accordance with the raster numbers n1, n2 and n3. For instance, the display screen (9) is controlled to display patterns of different pages on the four divided regions by the CPU (2). Otherwise, another interruption signal may be produced when the aforementioned coincidence signal is supplied to the CPU (2). |
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In [Figure 10], there is shown an apparatus for controlling the access of VRAM (7) in a second embodiment according to the invention. The apparatus comprises a CPU (2), a group of registers (53), an Address Counter (52), and VRAM (7). The group of registers (53) includes a Memory Address Write Register (3C), a Memory Address Read Register (3D), a VRAM Data Write Register (3E), a VRAM Data Read Register (3F), and a Control Register (3G) as shown in [Figure 3C to 3G]. The Memory Address Write Register (3C) and the Memory Address Read Register (3D) are connected to the Address Counter (52) so that the VRAM (7) is accessed in accordance with an address value of the Address Counter (52). Data are controlled to be written into the VRAM (7) and read therefrom by the CPU (2). The Control Register (3G) includes IW bits of bits 11 and 12 defining an Increment Width along with other bits as explained in [Figure 3G]. A relation between a content of bits 11 and 12 and an Increment Width is explained at the table on page 19 so that a repeated explanation is not made here. In a case where the IW bits are 0x00, an Increment Width is defined to be 0x01. If it is assumed that a starting address of the Memory Address Write Register (3C) is 0x00, data of the VRAM Data Write Register (3E) are written into a region of an address 0x00 of the VRAM (7) when the Address Counter (52) counts a predetermined number corresponding to the address 0x00. Then, an address of the Memory Address Write Register (3C) is incremented by 0x01 and therefore changed from 0x00 to 0x01. The data written into the VRAM (7) corresponds to data of the address 0x00 on the fictitious screen as shown in [Figure 4A]. Next, an address of the VRAM (7) is counted by the Address Counter (52) in accordance with a content 0x01 of the Memory Address Write Register (3C), and data of the VRAM Data Write Register (3E) are written into a region of an address 0x01 of the VRAM (7). In this manner, data corresponding to addresses 0x1F, 0x20 to 0x3F, 0x40 to 0x5F of horizontal directions of the fictitious screen are sequentially written into the VRAM (7). In a case where the IW bits are 0x01, an Increment Width is defined to be 0x20. If it is assumed that a starting address of the Memory Address Write Register (3C) is 0x00 data of the VRAM Data Write Register (3E) are written into a region of an address 0x00 of the VRAM (7) when the Address Counter (52) counts a predetermined number corresponding to the address 0x00. Then, an address of the Memory Address Write Register (3C) is incremented by 0x20 and therefore changed from 0x00 to 0x20. Next, an address of the VRAM (7) is counted by the Address Counter (52) in accordance with a content 0x20 of the Memory Address Write Register (3C), and data of the VRAM Data Write Register (3E) are written into a region of an address 0x20 of the VRAM (7). In this manner, data corresponding to addresses 0x00, 0x20, 0x40, 0x60 of the fictitious screen are sequentially written into the VRAM (7). As a result, it is said that the present operation is equal to an operation in which a pattern to be displayed in horizontal directions is changed to a pattern to be displayed in vertical directions. Otherwise, if it is assumed that an Increment Width is 0x40 or 0x80, a pattern which is enlarged by two times or four times and displayed in vertical directions is obtained. In addition, if an Increment Width is appropriately selected to be a predetermined value, an inclination, a rotation and so on of a pattern can be performed. Although the writing of data into the VRAM (7) is explained, the reading of data therefrom is also performed in the same manner as described above. Next, an apparatus for controlling the access of VRAM (7) in a third embodiment will be explained mainly in conjunction with [Figure 2] and [Figures 3A to 3U]. In a case where the CPU (2) is a data bus width of 16 bits, a chip selecting signal 0 is supplied to the terminal CS of the Video Display Controller (1) which is thereby enabled. A data bus width signal 0 is supplied through the terminal EX 8/16 to the control unit (20) of the Video Display Controller (1).
On the other hand, in a case where the CPU (2) is a data bus width of 8 bits, a chip selecting signal 0 is supplied to the terminal CS of the Video Display Controller (1) which is thereby enabled. A data bus width signal 1 is supplied through the terminal EX 8/16 to the control unit (20) of the Video Display Controller (1).
In the DMA transfer as described above, the source and destination addresses are incremented in the DMA Source Address Register (3R) and DMA destination Address Register (3S) by one in accordance with the content 0x00 of the bits 2 and 3 of the DMA Control Register (3Q). At the same time, a counting up or down is performed in a counter for counting the block length. When a counted value is equal to the block length, the DMA transfer is controlled to be finished. Although the DMA transfer is explained to be performed between two regions of the VRAM (7), it may be performed between the VRAM (7) and the Sprite Attribute Table buffer (23). In such a case, a starting address of a source address is defined in accordance with a content of the DMA VRAM-SATB Source Address Register (3U). |
Patent for VRAM access via VDC/CPU
Note: terminals with a High value are a binary 1 and Low is a binary 0.
United States Patent Number: 5030946APPARATUS FOR THE CONTROL OF AN ACCESS TO A VIDEO MEMORY
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In [Figure 1], there is shown an apparatus for displaying an image on a screen which is mainly composed of a Video Display Controller (1), a CPU (2), a Video Color Encoder (3), and a Programmable Sound Generator (4). The Video Display Controller (1) supplies the Video Color Encoder (3) with image data for a story which are read from a VRAM (7) under the control of the CPU (2) reading a program stored in a ROM (5). The CPU (2) controls a RAM (6) to store data, calculation or arithmetical results etc. temporarily in accordance with a program stored in the ROM (5). The Video Color Encoder (3) is supplied with image data to produce RGB analog signals or video color signals including luminance signals and color difference signals to which the RGB signals are matrix-converted by using color data stored therein. The programmable sound generator 4 is controlled by the CPU (2) reading a program stored in the ROM (5) to produce audio signals making left and right stereo sounds. The video color signals produced at the Video Color Encoder (3) are of composite signals supplied through an interface (8) to a video display (9), while the RGB analog signals are directly supplied to a video display (9) which is used as an exclusive monitor apparatus. The left and right analog signals supplied from the Programmable Sound Generator (4) are amplified at amplifiers 11a and 11b to make sounds at speakers 12a and 12b. |
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In [Figure 2A], there is shown the Video Display Controller (1) transferring data between the CPU (2) and VRAM (7) which comprises a control unit (20) including various kinds of registers to be described later, an address unit (21), a CPU read/write buffer (22), and sprite shift register (24), a background shift register (25), a data bus buffer (26), a synchronic circuit (27), and a priority circuit (28). The control unit (20) is provided with a BUSY terminal being Low to keep the CPU (2) writing data into the VRAM (7) or reading data therefrom in a case where the Video Display Controller (1) is not in time for the writing or reading of the date, an IRQ terminal supplying an interruption request signal, a CK terminal receiving a clock signal of a frequency for one pixel periods (one picture element), a RESET terminal receiving a reset signal for initializing the Video Display Controller (1), and an EX 8/16 terminal receiving a data bus width signal for selecting one of 8 and 16 bit data buses. The address unit (21) is connected to terminals MAO to MA15 supplying address signals for the VRAM (7) which has, for instance, a special address region of 65,536 words. The address unit (21), CPU read/write buffer (22), Sprite Attribute Table (23), sprite shift register (24), and background shift register (25) are connected to terminals MD 0 to MD 15 through which data are transferred to and from the VRAM (7). The Sprite Attribute Table buffer (23) is a memory for storing X and Y display positions, pattern codes and control data of sprites each composed of 16×16 pixels as described in more detail later. The sprite shift register (24) stores pattern and color data of a sprite read from a sprite generator in the VRAM (7) which is accessed in accordance with the pattern codes stored in the Sprite Attribute Table (23) as described in more detail later. The background shift register (25) stores pattern data, along with CG color, read from a character generator in the VRAM (7) in accordance with an address based on a character code of a background attribute table in the VRAM (7) which is accessed in an address decided by a raster position as also described in more detail later. The data bus buffer (26) is connected to terminals D0 to D15 through which data are supplied and received. In the Video Display Controller (1), 8 or 16 bit interface is selected to comply with a data width of a system including the CPU2 wherein the terminals D0 to D7 among the terminals D0 to D15 are occupied when the 8 bit interface is selected. The synchronic circuit (27) is connected to a DISP terminal indicating a display period, a VSYNC terminal from which a vertical synchronous signal for a video display (9) is supplied and in which an external vertical synchronous signal is received, and a HSYNC terminal from which a horizontal synchronous signal for a video display (9) is supplied and in which an external horizontal synchronous signal is received. The priority circuit (28) is connected to terminals VD0 to VD7 through which video signals are supplied, and a SP/BG (VD8) terminal being High when the video signals are of a sprite and being Low when the video signals are of a background. The aforementioned control unit (20) is also connected to a CS terminal being Low wherein the CPU (2) is able to read data from registers therein and sprite data thereinto, a RD terminal receiving a clock signal for the reading thereof, a WR terminal receiving a clock signal for the writing thereof, and terminals A0 and A1 which are connected to address bus of the CPU (2). Further, the Video Display Controller (1) is provided with a MRD terminal being Low when the CPU (2) reads data from the VRAM (7), and a MWR terminal being Low when the CPU (2) writes data into the VRAM (7). |
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In [Figure 2B], there is shown an apparatus for displaying a sprite on a screen which is included in the apparatus of [Figure 1] wherein the reference numerals 31 and 32 indicate a sprite attribute table and sprite generator in the VRAM (7) respectively. The Sprite Attribute Table (31) can include, for instance, sixty-four sprites, while the Sprite Generator (32) can include, for instance, one thousand and twenty-four sprites. In the Sprite Attribute Table (31), addresses of 0 to 63 are assigned to the sixty-four sprites to give a priority thereto in the order of the address 0>1>. . . >62>63. Each of the sprites is composed of 16×16 bits, and includes X and Y coordinates, pattern codes and control data. As to each of the sprites, the Y coordinate is compared with a raster signal supplied from a scanning raster producing circuit 33 in a coincidence detection circuit (34) whereby sprites each having a Y coordinate coincident with a raster signal are stored into a pattern code buffer (35) which can store a maximum number of 16 sprites by referring to a corresponding one of the addresses 0 to 63. A selector (36) selects a pattern code of the Sprite Attribute Table (31) in accordance with an address stored in the pattern code buffer (35) to access the Sprite Generator (32) in regard to an address which is of a selected pattern code, thereby reading pattern data from the Sprite Generator (32). The pattern data thus obtained are stored into a pattern data buffer (37) along with an X coordinate corresponding thereto read from the Sprite Attribute Table (31). The storing of sprites into the pattern code buffer (35) is performed at a horizontal display period preceding to the present horizontal display period by one scanning raster, while the storing of pattern data into the pattern data buffer (37) is performed at a following horizontal retrace period. When a scanning raster at which pattern data are displayed has come, the X coordinate thus stored in the pattern data buffer (37) is compared with a counted value of a horizontal pixel period clock counter 38 in a coincidence detection circuit (39) whereby pattern data having an X coordinate coincident with the counted value are supplied to a parallel/serial converting circuit (40). In the parallel/serial converting circuit (40), parallel pattern data are converted into serial pattern data which are supplied through a gate circuit (42) to a video display (9). The gate circuit (42) is controlled to be turned on and off in accordance with a content of a starting coordinates registration circuit (43) by the CPU (2). The content thereof is X and Y coordinates by which the starting coordinates of a display region is defined on a display screen. |
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| In [Figures 3A to 3U], there are shown various kinds of registers included in the Control Unit (20) of the Video Display Controller (1). (a) Address Register ([Figure 3A]) A register number AR is exclusive written into the address register designating one of the memory address write register to DMA VRAM-SATB source address register as shown in [Figures 3C to 3U] so that data are writing into the Video Display Controller (1) under the condition that the A1 and CS terminals thereof are Low. In a case where 16 bit data bus is selected, the EX 8/16 terminal is 0, the A1 terminal is 0, the R/W terminal is W, and the A0 terminal is no matter. In a case where 8 bit data bus is selected, the EX 8/16 terminal is 1, the A0 and A1 terminals are 0, and the R/W terminal is W. | |
| (b) Status Register ([Figure 3B]) A bit corresponding to one of interruption jobs is set to be High in the status register to make the interruption active when a cause of the interruption which is enabled by an interruption permission bit of a Control Register and DMA Control Register as showing in [Figures 3G and 3Q] is occurred. When the status is read from the status register, the corresponding bit is cleared automatically. The status indicating bits are as follows. (1) bit 0 (CR) - collision of sprites It is indicated that the sprite number 0 of a sprite is collided with any one of the sprite numbers 1 to 63 of sprites. (2) bit 1 (OR) - more sprites than a predetermined number (2.1) a case where more than 17 sprites are detected on a single raster line. (2.2) a case where data of a sprites which is designated are not transferred to a data buffer in a horizontal trance period. (2.3) a case where a bit of CGX in control data of a sprite by which two sprites are joined in a horizontal direction is set so that data of the sprites are not transferred to a data buffer. (3) bit 2 (PR) - detection of raster It is indicated that a value of a raster counter becomes a predetermined value of a raster detecting register. (4) bit 4 (DS) - finishing of DMA transfer It is indicated that data transfer between the VRAM (7) and Sprite Attribute Table buffer (23) is finished. (5) bit 4 (DV) - finishing of DMA transfer It is indicated between two regions of VRAM (7) is finished. (6) bit 5 (VD) - vertical retrace period It is indicated that the VRAM (7) accessed for the writing or reading of data by the CPU (2) so that the BUSY terminals is 0. | |
| (c) Memory Address Write Register (register name 0x00, [Figure 3C]) A starting address MAWR is written into the memory address write register so that the writing of data begins at the starting address of the VRAM (7). | |
| (d) Memory Address Read Register (register number 0x01, [Figure 3D]) A starting address MARR is written into the memory address read register. When the upper byte of the starting address is written thereinto, data are begun to be read from the starting address of the VRAM (7) so that data thus read are written into a VRAM data read register as showing in [Figure 3F]. There after, the starting address MARR is automatically incremented by one. | |
| (e) VRAM Data Write Register (register number 0x02, [Figure 3E]) Data which are transferred from the CPU (2) to the VRAM (7) are written into the VRAM data write register. When the upper byte of the data VWR is written thereinto, the Video Display Controller (1) begins to write the data into the VRAM (7) and the address MAWR of the memory address write register is automatically incremented by one upon writing of the data. | |
| (f) VRAM Data Read Register (register number 0x02, [Figure 3F]) Data which are transferred from the VRAM (7) to the CPU (2) are written into the VRAM data read register. When the upper byte of the data VRR is read therefrom, the reading of data is performed at the following address of the VRAM (7). | |
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(g) Control Register (register number 0x05, [Figure 3G])
An operating mode of the Video Display Controller (1) is controlled in accordance with the
following bits of the Control Register.
(1) bits 0 to 3 (IE) - enable of interruption request
(1.1) bit 0 - collision detection of sprites
(1.2) bit 1 - excess number detection of sprites
(1.3) bit 2 - raster detection
(1.4) bit 3 - detection of vertical retrace period
(2) bits 4 and 5 (EX) - external synchronization
(3) bit 6 (SB) - sprite blanking
It is decided whether a sprite should be displayed on a screen or not.
The control of the bit is effective in the following Horizontal Display Period.
(3.1) 0 - blanking of a sprite
(3.2) 1 - display of a sprite
(4) bit 7 (BB) - background blanking
It is decided whether background should be displayed on a screen or not.
The control of the bit is effective in the following Horizontal Display Period.
(4.1) 0 - blanking of background
(4.2) 1 - display of background.
(3.4) As a result, when bits 6 and 7 are both 0, there is a resulted "burst mode" in
which the following operations can be performed.
(3.4.1) The access to the VRAM (7) is not performed for a display, but the VRAM (7) is
accessed by the CPU (2).
(3.4.2) DMA between two regions of the VRAM (7) is possible to be performed at any
time.
In such occasions, the terminals VD0 and VD7 are all Low while the SP/BG terminal is
High. On the other hand, when the bits 6 and 7 are both 1, there is released from
the "burst mode".
(5) bits 8 and 9 (TE) - selection of DISP terminal outputs
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| (h) Raster Detecting Register (register number 0x06, [Figure 3H]) A raster number RCR at which an interruption job is performed is written into the raster detecting register. An interruption signal is produced when a value of a raster counter is equal to the raster number RCR. The raster counter is preset to be 64 at a preceding scanning raster line to a display starting raster line as described in more detail later, and is increased at each raster line by one. | |
| (i) BGX Scroll Register (register number 0x07, [Figure 3I]) The BGX scroll register is used for a horizontal scroll of background on a screen. When a content BXR is rewritten therein, the content is effective in the following raster line. | |
| (j) BGY Scroll Register (register number 0x08, [Figure 3J]) The BGY scroll register is used for a vertical scroll of background on a screen. When a content BYR is rewritten therein, the content is effective to be as "BYR + 1" in the following raster line. | |
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(k) Memory Width Register (register number 0x09, [Figure 3K])
(1) bits 0 and 1 (VM) - VRAM pixel width
A pixel width in which an access to the Background Attribute Table and character
generator, DMA and access of the CPU (2) to the VRAM (7) during a horizontal display
period are performed is written into the bits of the memory width register. The pixel
width is decided dependent on a memory speed of the VRAM (7). When the bits 0 and 1
are re-written therein, the content is effective at the beginning of a vertical
retrace period.
BAT is for Background Attribute Table, and CG is for character generator.
(2) bits 2 and 3 (SM) - sprite pixel width
A pixel width which an access to the sprite generator is performed during a horizontal
retrace period is written into the bits of the memory width register.
(3) bits 4 to 6 (SCREEN)
The number of character in X and Y directions of a fictitious screen is decided
dependent on the content of the bits. When a content is effective at the beginning
of a vertical retrace period.
(4) bit 4 (CM) - CG mode When a VRAM pixel width is of 4 pixels, a color block of a character generator is changed dependent on the bit. A content is writtent into the bit, the content is effective in the following raster line. |
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| (l) Horizontal Synchronous Register (register number 0x0A, [Figure 3L]) (1) bits 1 to 4 (HSW) - horizontal synchronous pulse A pulse width of Low level of a horizontal synchronous pulse is set as an unit of a character cycle. One of 1 to 32 is selected by using 5 bits to comply with the specification of a video display. (2) bits 8 to 14 (HDS) - starting position of horizontal display A period between a rising edge of a character cycle. An optimum position in a horizontal direction on a video display is decided by a content of the 7 bits. When it is assumed that a horizontal display position (horizontal back porch) is N, N - 1 is written into HDS bits. | |
| (m) Horizontal Display Register (register number 0x0B, [Figure 3M]) (1) bits 0 to 6 (HDW) - horizontal display width A display period in each raster line is set as an unit of a character cycle, and is decided in accordance with the number of characters in the horizontal direction on a video display dependent on a content of the 7 bits. If it is assumed that a horizontal display position is N, N - 1 is written into HDW bits. (2) bits 8 to 11 (HDE) - horizontal display ending position A period between an ending of a Horizontal Display Period and a rising edge of a horizontal synchronous signal is set as an unit of a character cycle. An optimum position of a horizontal display is set on a video display by the 7 bits. When it is assumed that a horizontal display ending position (horizontal back porch) is N, N -1 is written into HDE bits. | |
| (n) Vertical Synchronous Register (register number 0x0C, [Figure 3N]) (1) bits 0 to 4 (VSW) - vertical synchronous pulse width A pulse width of a vertical synchronous signal is decided in a width of Low level as a unit of a raster line. One of 1 to 32 is selected to comply with a specification of a video display. (2) bits 8 to 15 (VDS) - vertical display starting position A period between a rising edge of a vertical synchronous signal and a vertical synchronous starting position is set as an unit of a raster line. When it is assumed that a vertical display starting position (vertical back porch) is N, N-2 is written into the bits. | |
| (o) Vertical Display Register (register number 0x0D, [Figure 3O]) A vertical display period (display region) is set as an unit of a raster line. A vertical display width is decided in accordance with the number of raster lines to be displayed on a video display which is defined by a content of the 9 bits. When it is assumed that a vertical display width is N, N - 1 is written into the VDW bits. | |
| (p) Vertical Display Ending Position Register (register number 0x0E, [Figure 3P]) A period between a vertical display ending position and a rising edge of a vertical synchronous signal is set as an unit of a raster line. When it is assumed that a vertical optimum position (vertical front porch) is N to be defined by the 8 bits, N is written into the VCR bits. | |
| (q) DMA Control Register (register number 0x0F, [Figure 3Q]) (1) bit 0 (DSC) - Enable an interruption at the finishing of transfer between the VRAM (7) and Sprite Attribute Table buffer (23). It is decided whether or not an interruption is enabled at the finishing time of the transfer. (1.1) 0 - disable (1.2) 1 - enabled (2) bit 1 (DVC) - Enable an interruption at the finishing of transfer between two regions of the VRAM (7). It is decided whether or not an interruption is enabled finishing time of the transfer. (2.1) 0 - disable (2.2) 1 - enabled (3) bit 2 (SI/D) - Increment/decrement of a source address One of automatically increment and decrement of a source address is selected in a transfer between two regions of VRAM (7). (3.1) 0 - increment (3.2) 1 - decrement (4) bit 3 (DI/D) - Increment/decrement of a destination address One of automatically increment and decrement of a destination address is selected in a transfer between two regions of VRAM (7). (4.1) 0 - increment (4.2) 1 - decrement (5) bit 4 (DSR) - repetition of a transfer between the VRAM (7) and the Sprite Attribute Table buffer (23) is enabled. (5.1) 0 - disable (5.2) 1 - enabled | |
| (r) DMA Source Address Register (register number 0x10, [Figure 3R]) A starting address of a source address is allocated in a transfer between two regions of the VRAM (7). | |
| (s) DMA Destination Address Register (register number 0x11, [Figure 3S]) A starting address of a destination address is allocated in a transfer between two regions of the VRAM (7). | |
| (t) DMA Block Length Register (register number 0x12, [Figure 3T]) A length of a block is defined in a transfer between two regions of the VRAM (7). | |
| (u) DMA VRAM-SATB Source Address Register (register number 0x13, [Figure 3U]) A starting address of a source address is allocated in a transfer between the VRAM (7) and Sprite Attribute Table buffer (23). | |
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In [Figure 4A, there is shown an address in a background attribute table for a character on a fictitious screen. A character and color to be displayed at each character position are stored in the background attribute table. A predetermined number of background attribute tables are stored in a region the first address of which is 0 in the VRAM (7). The fictitious screen shown therein which is one example is of 32×32 characters (1F=32). |
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In [Figure 4B, there is shown a screen which is framed by writing respective predetermined values into the aforementioned horizontal synchronous register, horizontal display register, vertical synchronous register and vertical display register as shown in [Figures 3L, 3M, 3N and 3O]. Although the respective predetermined values for the registers are not explained here, a display region is defined in accordance with "HDW+1" in the horizontal display register and "VDW+1" in the vertical display register. In the embodiment, the starting coordinates (x,y) for the display region is indicated to be as (32, 64). |
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In [Figures 5A and 5B], there are shown background attribute tables (BATs) in the VRAM (7) each of 16 bits to have a character code of lower 12 bits for designating a pattern number of a character and a CG color of upper 4 bits for designating a CG color code. |
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[Figures 6A and 6B] |
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[Figure 7] |
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[Figure 8] |
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[Figure 10] |
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In [Figure 11A] , there is shown an apparatus for the control of an access to a video memory in an embodiment according to the invention. The apparatus for the control of an access to a video memory comprises an oscillator (51) for producing oscillation signals, a frequency divider (52) for dividing a frequency of the oscillation signals by a predetermined dividing ratio to produce pixel clock signals, a memory width register (3K) as already explained in [Figure 3K] having a content of a number of pixel periods dependent on a memory speed of the VRAM (7), a number of pixel periods decision circuit (53) for deciding a pixel width in accordance with the content of the memory width register (3K), means (54, 55 and 56) for producing a CPU address signal, DMA address signal and CG address signal respectively to designate addresses in an access to the VRAM (7), an address selector (57) for selecting an address at an access timing which is set by the number of pixel periods decision circuit (53), and a data latch circuit (58) for latching data read from the VRAM (7). The VRAM (7) is shown in [Figure 11A] to include a VRAM region (33) of a fictitious screen as described in [Figure 4A] and a Character Generator (34) which is also shown in [Figure 11B]. One character of the Character Generator (34) is composed of four facets CH0 Ch1, CH2 and CH3 each having 8×8 pixels by which a pattern is defined by 16 words of 8 words for the facets CH0 and CH1 and other 8 words for the facets CH2 and CH3. The characters are addressed by the first addresses of the facets CHOs shown by A0, A1, A2 . . . which are defined by character codes of background attribute tables as described in [Figures 5A and 5B]. In operation, when a horizontal display of the scanning raster number 0 is started, the VM bits of the memory width register (3K) are checked by the number of pixel periods decision circuit (53). If it is assumed that a content of the VM bits is 00, a number of pixel periods of an access to the VRAM (7) is decided to be 1 as defined in the table on page 19. Accordingly, the VRAM (7) is accessed in accordance with a CPU address signal from the CPU address signal means (54) under the control of the address selector (57) at the first pixel timing among 8 pixels of one character cycle. Next, the VRAM region (33) of the VRAM (7) is accessed at an address 0 in accordance with a CG address signal from the CG address signal means (56) at the second pixel timing. At this moment, a character code and a CG color are read from a background attribute table, as shown in [Figures 5A and 5B], of the address 0. Thereafter, accesses are performed from the CPU (2 in [Figure 1]) to the VRAM (7) at the third and fifth pixel timings except for the fourth pixel timing, and the Character Generator (34) is accessed at the sixth pixel timing. In the access to the Character Generator (34), a CG address signal of the CG address signal means (56) is determined in accordance with a pattern number corresponding to a character code which is previously checked whereby display data are read from the facets CH0 and CH1 thereof. After the seventh pixel timing, display data are further read from the facets CH2 and CH3 in accordance with the same address signal at the 8 pixel timing. As a result, one character is formed in accordance with the display data of the four facets CH0 to CH3 which are latched in the data latch circuit (58). A display of the address 0 is performed on the video display (9 in [Figure 1]) in accordance with the data thus latched in the data latch circuit (58) wherein a color of the display is determined by the CG color in the background attribute table. In the horizontal displays which follow the horizontal display of the scanning raster line 0, the same operation as explained above will be repeated. On the other hand, if it is assumed that a content of the VM bits is 01, 10 or 11, the VRAM (7) is accessed with a number of pixel periods is 2, 2 or 4. For this reason, a content of the VM bits is determined dependent on a memory speed of the VRAM (7). In another operation, it is assumed that a content of the VM bits is 00 in the memory width register (3K) to provide a number of pixel periods of one pixel, and that a content of the IW bits is 00 in the control register as shown in [Figure 3G] to provide an address increment width 1. An operation in which data are written into the VRAM (7) is started after the first address for writing the data is written into the memory address write register as shown in [Figure 3C]. When the VRAM (7) is accessed from the CPU (2) as shown in [Figure 12] by the indication CPU→VRAM, the data are held in the CPU read/write buffer (22 in [Figure 2A]), if the writing of the data is collided in regard to its timing with a display cycle of the VRAM (7). For this reason, the CPU (2) is released from the writing of the data as changed from 0 to 1 in regard to a timing chart of CPU→VRAM. Thereafter, when the display cycle of the VRAM (7) is finished, the data thus held in the CPU read/write buffer (22) are written, as shown by the indication VRAM WR, into the VRAM (7) at the address which is designated by the memory address write register of [Figure 3C]. At this moment, a content of the memory address write register is incremented by one. On the other hand, in a case where the VRAM (7) is accessed from the CPU (2) when data are held in the CPU read/write buffer (22), the condition WAIT becomes effective in the CPU (2) so that a wait signal is produced at the BUSY terminal connected to the control unit (20 in [Figure 2A]). Therefore, the condition WAIT is much decreased in the number of occurrences in accordance with the provision of the CPU read/write buffer (22). In the same manner as described above, the VRAM (7) is accessed from the CPU (2) so that data are read from the VRAM as shown in [Figure 12] by the indication CPU ← VRAM. Data which are read from the VRAM (7) at an address designated by the memory address read register as shown in [Figure 3D] are once held in the CPU read/write buffer (22), when the access to the VRAM (7) is collided with the display cycle of the VRAM (7). When the display cycle of the VRAM (7) is finished, the data thus held in the CPU read/write buffer (22) are transferred to the CPU (2) as shown by the indication VRAM RD. At this moment, a content of the memory address read register is incremented by one. Otherwise, if the CPU read/write buffer (22) is not provided, the condition WAIT is increased in the number of occurrences as shown in [Figure 13] so that a throughput of the CPU (2) is decreased. In more detail, the condition WAIT is continued in the CPU (2) until the display cycle of the VRAM (7) is finished, when the VRAM (7) is accessed from the CPU (2) for the writing of data (CPU→VRAM) and the reading thereof (CPU ← VRAM) during that cycle. When the display cycle of the VRAM (7) is finished, data are written into the VRAM (7) as shown by the indication VRAM WR, and read from the VRAM as shown by the indication VRAM RD whereby flickers are prevented from being occurred on a screen. |
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Patent for 1-Bit Fonts
United States Patent Number: 5838295METHOD FOR SCROLLING IMAGES ON A SCREEN
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Before explaining a method for scrolling images on a screen of the preferred embodiment according to the invention, the aforementioned background of the invention will be again explained. In a computer system which is used in the invention, two kinds of image frames defined background and sprite are combined to provide one image frame, wherein the background image frame is composed of patterns defined character. In the following explanation, the character is composed of 8 |
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[Figure 1] shows a display screen which is defined by values set in registers, in which the horizontal set values are defined by the number of characters, and the vertical set values are defined by the number of rasters. The registers are for HSW (horizontal sync pulse width) HDS (horizontal display start position), HDW (horizontal display width), HDE (horizontal display end position), VSW (vertical sync pulse width), VCR (vertical display end position), VDW (vertical display period), and VDS (vertical display start position). |
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[Figure 2] shows a virtual screen which is composed of 32 to which addresses 0, 1, 2, . . . are assigned. |
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[Figure 3] shows a background attribute table (BAT) having a capacity equal to the addresses of the virtual screen which is a portion of a VRAM. The BAT stores at each address corresponding to each address of the virtual screen a set of a character code and a CG color, as explained next. |
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[Figure 4] shows the set of the character code (12 bits) for defining a pattern of a character, and the CG (4 bits) for defining a color. |
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[Figure 5] shows a Character Generator (CG) region which is also a portion of the VRAM. The CG regions is composed of CGs each having four facets CH0, CH1, CH2 and CH3 designated in group by the character code of the BAT. The first and second facets CH0 and CH1 provide first 8 words CG0, and the third and fourth facets CH2 and CH3 provide second 8 words CG1 as shown therein. As shown therein, each of the four facets CH0 to CH3 is composed of 8 bits, so that a 4 bit signal is obtained to combined with the 4 bit CG color, thereby providing an address signal of 8 bits for a memory called "a color pallet". The display control of the background is carried out in a horizontal display period, as explained below by use of [Figures 6 to 10A and 10B. |
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In [Figure 6], a position of a raster is detected in an address unit (10) to generate an address signal on the virtual screen as shown in [Figure 2], by which the BAT 21 of the VRAM (20) is accessed to provide a character code and a CG color as shown in [Figure 4]. The character code is supplied to the address unit (10) to generate an address signal for accessing the CG region 22 of the VRAM (20), and the CG color is supplied to be stored in a CG color shift register 31 of a background shift register (30). A color pallet 41 supplies color signals. |
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In [Figure 7], the CG region 22 is accessed by the address unit (10), so that the first two facets CH0 and CH1 are supplied to be stored in first and second shift registers 32 and 33 of the background shift register (30). |
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In [Figure 8], the second two facets CH2 and CH3 are read from the same address of the CG region 22 to be stored in third and fourth registers 34 and 35 of the background shift register (30). |
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In [Figure 9], the 4 bit CG color is supplied from the CG color shift register 31, and 1 bit is supplied from each of the shift registers 32 to 35 to provide a 4 bit signal, so that an 8 bit address signal VD0 to VD7 is generated to be supplied through a priority circuit (40) to a color pallet 41 |
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[Figure 10A] shows the 8 bit address signal VD0 to VD7, to which a bit VD8 is combined, wherein the background is displayed by 0 of VD8, while a sprite is displayed by 1 of VD8. |
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[Figure 10B] shows a display output during a period of retrace, in which the bit VD8 is 1, and the bits VD0 to VD7 are 0. For the display of sprites, a sprite shift register (50) is used to store sprite data. In a display as described above, vertical and horizontal smooth scrolling are carried out by use of registers called BGY and BGX scroll registers (not shown), in which scroll data are stored. The vertical scroll can be performed by a unit of rasters, and the horizontal scroll can be performed by a unit of pixels. In the vertical scroll based on the unit of rasters, a scroll can not be carried out character by character. On the other hand, a horizontal scroll can be done character by character, because the horizontal scroll is carried out pixel by pixel. In this case, however, a method of a raster interruption must be adopted. As a result, the setting of a timing becomes difficult. This is one of disadvantages which is overcome by the invention. Next, a method for scrolling images on a screen of the preferred embodiment according to the invention will be explained in [Figures 11A to 11D. |
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[Figure 11A] shows a character pattern No. 1 of 8 squarely closed belt shape 100 (simply defined mark hereinafter), and [Figures 11B to 11D show character patterns No. 2 to No. 4 of the same size having marks 100, each position of which is shifted in the vertical direction by two pixels. In operation, the character patterns No. 1 to No. 4 are in order displayed at an addressed position(s) selected from the addresses 0, 1, 2, of the virtual screen ([Figure 2]) in accordance with the process using the BAT 21 and the CG region 22 of the VRAM (20), the background shift register (30), the color pallet, etc. as explained before, so that the vertically scrolling display of the mark is carried out at the selected address position on the screen, wherein the mark moves downwardly. On the other hand, the mark moves in the upper direction, in case where the character patterns are displayed in the order of No. 4 to No. 1. This scroll is carried out by a program stored in a ROM (not shown), and is defined "artificial scroll" which is discriminated from a smooth scroll which is carried out by a system (hardware). The smooth scroll must be carried out on a whole plane of the screen, while the artificial scroll can be carried out on a limited portion of the screen and on different portions thereof by using character patterns having different marks. The artificial scroll using the different marks is defined "artificial multiple scroll", in which scrolls may be carried out in any direction such as vertical, horizontal, and inclination directions by using character patterns having predetermined shifted marks. In realizing an inclination scroll by using the smooth scroll, vertical and horizontal scrolls must be combined. However, it can be carried out directly by using the artificial multiple scroll of the invention. [Figures 12A to 12D shows character patterns No. 1 to No. 4 of 8 having marks 100, by which the inclination scroll can be carried out. The mark moves in the upper left to lower right direction by displaying the character patterns in the order of No. 1 to No. 4, while the marks moves in the lower right to upper left direction by displaying them in the order of No. 4 to No. 1. [Figures 13A and 13B shows a display of a valley 200 of V shape having stones 210A on the bottom and 210B and 210C on the outside. A plurality of characters display large and small sizes in order to provide a perspective representation in a display pattern. Also, in order to provide viewers with a three-dimensional sense on this display, the bottom stones 210A are controlled to move slowly as compared to the outside stones 210B and 210C, if it is assumed that the viewers look down the valley 200 from an airplane. In addition, the stones 210A are preferably displayed to be smaller as compared to the outside stones 210B and 210C. |
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[Figure 14A] shows the bottom and outside stones 210A, 210A', 210B, 210B' and 210C displayed on a right half portion of the screen having a dotted line A for an original position in accordance with the method as explained in [Figures 13A and 13B. As understood from the illustration in [Figure 14A], the bottom stone 210A occupies one character (8 210A', 210B, 210B' and 210C occupy 4 characters, 9 characters, 16 characters, and 36 characters in terms of area. That is, the stones 210A to 210C occupy 16 characters in the horizontal direction on the right half portion of the screen. In the vertical direction, a predetermined number of the bottom stones 210A are arranged to contact with upper and lower ones. Other stones 210A' to 210C are arranged in the vertical direction in the same manner as those 210A. In this assumption, the vertical smooth scroll is carried out in the lower direction in accordance with a rate of 6 pixels during a period of 1V which is a unit of the detection number in a vertical retrace period. In this preferred embodiment, the period of 1V is 1/60 sec. In addition to the vertical smooth scroll, the artificial multiple scroll is applied to the display of the valley in accordance with the invention. That is, four pixels artificial vertical scroll is carried out for the bottom stones 210A, three pixel artificial vertical scroll for the stones 210A', two pixel artificial vertical scroll for the stones 210B, one pixel artificial vertical scroll for the stones 210B', and no artificial vertical scroll for the stones 210C, respectively, in the upper direction, as shown in [Figure 14A] by arrows. The resultant scroll values are obtained in a below table. ______________________________________ SMOOTH ARTIFICIAL RESULTANTSTONES SCROLL SCROLL SCROLL______________________________________210A +6 -4 +2210A' +6 -3 +3210B +6 -2 +4210B' +6 -1 +5210C +6 0 +6______________________________________ In accordance with the resultant vertical scroll, the stones 210A to 210C moves downwardly by pixels as shown in [Figure 14B], when a time has been elapsed by 3V(=3/60 sec). In [Figure 14], the pixel amounts are indicated by three times of the resultant scroll values. Consequently, the display of the valley provides viewers with cubic sense having the depth and power of images. In accordance with a smooth scroll conducted by a system, an operation is required to comply with an algorithm of the system. On the other hand, an artificial multiple scroll of the invention is carried out by a user program, so that the flexibility is obtained in operation. As explained in the preferred embodiment, a vertical scroll can be carried out character by character. This has a significant meaning in accordance with the combination of the vertical smooth scroll which is carried out raster by raster. Consequently, there is a significant advantage in providing motion pictures having the depth. In an ordinary display of a background, characters of a small number in kind are used to decrease a capacity of a memory. The artificial multiple scroll of the invention complies with the requirement of suppressing a memory capacity in a home TV game system. Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth. |
