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The Hudson Soft HuC6280 is the 8-bit CPU of NEC's PC Engine console. It contains a customized version of a 65SC02 core, a timer, and sound generation hardware. The HuC6280 is referred to as "Dr. Pepper" or "DRP" by NEC-HE.


The HuC6280 contains a 65C02 core which has several enhancements.

The processor operates at two speeds, 1.78 MHz and 7.16 MHz.

HuC6280's PSG

The PSG (Programmable Sound Generator) provides 6 sound channels, which can be conveniently paired according to the functionality they provide:

      0-1 - Waveform playback
            Frequency modulation (channel 1 muted)
      2-3 - Waveform playback only
      4-5 - Waveform playback
            White noise generation

Waveform playback is the most common and allows a 32 byte, 5 bit unsigned linear sample to be played back at selected frequencies. Frequency modulation takes this one step further, allowing the playback frequency to be dynamically adjusted according to a specified pattern. White noise is used to simulate percussion instruments and effects, such as explosions, by means of a pseudo-random square wave.

Alternatively, each channel can be individually switched to "Direct D/A" mode in which the programmer can send data directly to the sound mixer, allowing more complex sound patterns to be generated, such as speech. Inevitably, this requires more programming effort and CPU time.

Memory mapping

The HuC6280 has a 64 KB logical address space and a 2 MB physical address space. To access this entire memory space, the HuC6280 uses an MMU (Memory Management Unit) that splits the memory space into segment of 8 KB. The logical address space is split as follows:

Each logical 8 KB segment (or page) is associated with an 8-bit register (MPR0-7) that contains the index of the 8 KB segment (or bank) in physical memory to map in this page.

Memory Map

The HuC6280 can address 21 bits (2MB) of physical memory but uses 16-bit logical addresses (e.g. LDA $8020). The 64KB logical address space is split into eight 8KB segments. The location within this segment is defined by the lower 13 bits of the logical address. The remaining upper three bits are are used to select the MPR (Mapped Page Register). Each 8KB segment (of the 64KB logical addressing space) has a corresponding 8-bit "MPR" register, which is used to create a 21-bit(13 lower bits of logical address + 8 bits of corresponding MPR) address sent over the bus.

PhysicalAddress = (LogicalAddress AND 0x1FFF) OR ( MPR[LogicalAddress / 0x2000] * 0x2000 )

MPR Logical Memory Range
0 $0000 - $1FFF
1 $2000 - $3FFF
2 $4000 - $5FFF
3 $6000 - $7FFF
4 $8000 - $9FFF
5 $A000 - $BFFF
6 $C000 - $DFFF
7 $E000 - $FFFF

Only two instructions are used to access these registers:


The HuC6280's timer operates off of the 7.1591MHz clock. This clock is first sent into a divide-by-1024 counter, and the output of the clock divider is used to decrement the timer counter register, if the timer is enabled. When the timer counter register decrements when its value is 0, the timer counter will reload with the value contained in the timer latch, and the timer's IRQ line is activated. The timer's IRQ vector is located at logical address $FFFA. The timer IRQ can be acknowledged(IE the timer's IRQ line made inactive again to prevent future interrupts) by reading from the IRQ mask register, or writing to the read-only IRQ status register.

Address(in I/O page) R/W Bits Description
$0C00 R Bit 0 - 6 Current timer counter value.
Bit 7 (Undefined, I/O data buffer D7)
W Bit 0 - 6 Timer latch value.
Bit 7 Unused
$0C01 W Bit 0 Timer enabled if set to 1. Writing 0, then 1, will force a reload of the timer counter from the timer latch and reset the divide-by-1024 counter.
Bit 1 - 7 Unused


The HuC6280

Pin Signal Direction Description
1 A5 out Address bit 5
2 A4 out Address bit 4
3 A3 out Address bit 3
4 A2 out Address bit 2
5 A1 out Address bit 1
6 A0 out Address bit 0
7 GND s Ground
8 +5V s Supply
9 XOUT out Output that follows XIN polarity, different pulse shape
10 XIN in 21.477270 MHz clock input (OSC1)
11 /RESET in Reset signal input
12 RDY in Induce wait state while pulled low
13 SX out Complementary CPU clock output (7.16 or 1.79 MHz)
14 HSM out High Speed Mode (1= 7.16, 0= 1.78 MHz)
15 +5V s Supply
16 GND s Ground
17 LOUT out Audio output, left channel
18 ROUT out Audio output, right channel
19 VCC s (+5V)
20 VEE s (+2.5V)
21 AGND s (GND)
22 K0 in Input port K ($1000.D0)
23  ??? out Unknown. Looks like a combination of SX, BSY, A0.
24 K1 in Input port K ($1000.D1)
25 K2 in Input port K ($1000.D2)
26 K3 in Input port K ($1000.D3)
27 K4 in Input port K ($1000.D4)
28 K5 in Input port K ($1000.D5)
29 K6 in Input port K ($1000.D6)
30 K7 in Input port K ($1000.D7)
31 O0 out Output port O ($1000.D0)
32 O1 out Output port O ($1000.D1)
33 O2 out Output port O ($1000.D2)
34 O3 out Output port O ($1000.D3)
35 O4 out Output port O ($1000.D4)
36 O5 out Output port O ($1000.D5)
37 O6 out Output port O ($1000.D6)
38 O7 out Output port O ($1000.D7)
39  ??? Always '1'
40  ??? Always '1'
41  ??? Always '1'
42  ??? Always '1'
43 /IRQ2 in IRQ2 interrupt input
44 /IRQ1 in IRQ1 interrupt input
45 /NMI in NMI interrupt input
46 SYNC out Memory read type; 1= Opcode fetch, 0= Not opcode fetch
47 +5V s Power supply
48 GND s Ground
49 D0 in / out Data bus, bit 0
50 D1 in / out Data bus, bit 1
51 D2 in / out Data bus, bit 2
52 D3 in / out Data bus, bit 3
53 D4 in / out Data bus, bit 4
54 D5 in / out Data bus, bit 5
55 D6 in / out Data bus, bit 6
56 D7 in / out Data bus, bit 7
57 +5V s Power supply
58 GND s Ground
59 /CEK out HuC6260 /CS (@ FF:0400-0700)
60 /CE7 out HuC6270 /CS (@ FF:0000-03FF)
61 /CER out Work RAM /CS (@ F8:0000-1F00)
62 /RD out Memory read strobe
63 /WR out Memory write strobe
64 A20 out Address bus, bit 20
65 A19 out Address bus, bit 19
66 A18 out Address bus, bit 18
67 A17 out Address bus, bit 17
68 A16 out Address bus, bit 16
69 A15 out Address bus, bit 15
70 A14 out Address bus, bit 14
71 A13 out Address bus, bit 13
72 A12 out Address bus, bit 12
73 A11 out Address bus, bit 11
74 A10 out Address bus, bit 10
75 GND s Ground
76 +5V s Power supply
77 A9 out Address bus, bit 9
78 A8 out Address bus, bit 8
79 A7 out Address bus, bit 7
80 A6 out Address bus, bit 6

According to the patents, test terminals /EA1, /EA2, /EA3, /EAT should be present. They probably correspond to the unknown pins. Based on information from Charles MacDonald.