View source for HuC6280 Instruction Set

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== ADC - Add with Carry ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || ? || 0 || || || ? || ?
|}
<p>Add the value specified by the operand, and 1 if the Carry flag is set, to the value in the accumulator.  If the result is too large to fit in the accumulator, the carry flag will be set, otherwise it will be cleared.</p>
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).</p>
<p>The overflow flag is not affected by this instruction if in Decimal mode; otherwise, if bit 7 of the result != bit  7 of the accumulator before the operation, and bit 7 of the accumulator before the operation == bit 7 of the value specified by the operand, the overflow flag is set, otherwise it is cleared.  In other words, if we were to treat the accumulator and value specified by the operand as [http://en.wikipedia.org/wiki/Two%27s_complement two's complement] numbers, in the range of -128 to 127, the overflow flag will be set if the end result is outside of this range(otherwise it will be cleared).</p>
<p>If T=1 (the previous instruction is SET) the zero-page byte specified by the X register is used instead of the A register.</p>

<p>Here is a recap of the status register after use :</p>
{|
|-
| N || Negative Flag || Set if bit 7 is set
|-
| V || Overflow Flag || Set if bit 7 (sign bit for 2's complement number) is incorrect
|-
| T || T Flag || 0
|-
| D || Decimal Flag || N/A
|-
| I || Interrupt Disable || N/A
|-
| Z || Zero Flag || Set if A == 0
|-
| C || Carry Flag || Set if overflow in bit 7 occured
|-
|}


{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || ADC #$ii || $69 || 2 || 2
|-
| Zero Page || ADC $zz || $65 || 2 || 4
|-
| Zero Page, X || ADC $zz,X || $75 || 2 || 4
|-
| Absolute || ADC $aaaa || $6d || 3 || 5
|-
| Absolute, X || ADC $aaaa,X || $7d || 3 || 5
|-
| Absolute, Y || ADC $aaaa,Y || $79 || 3 || 5
|-
| Indirect || ADC ($zzzz) || $72 || 3 || 7
|-
| Indexed Indirect || ADC ($zz,X) || $61 || 2 || 7
|-
| Indirect, Index || ADC ($zz),Y || $71 || 2 || 7
|}

== AND - AND Accumulator with Memory ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}

Performs a bit by bit logical and on the accumulator with the value specified by the operand.

<p>Here is a recap of the processor status flags after use :</p>
{|
|-
| N || Negative Flag || Set if bit 7 is set
|-
| V || Overflow Flag || N/A
|-
| T || T Flag || 0
|-
| D || Decimal Flag || N/A
|-
| I || Interrupt Disable || N/A
|-
| Z || Zero Flag || Set if A == 0
|-
| C || Carry Flag || N/A
|-
|}


{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || AND #$ii || $29 || 2 || 2
|-
| Zero Page || AND $zz || $25 || 2 || 4
|-
| Zero Page, X || AND $zz,X || $35 || 2 || 4
|-
| Absolute || AND $aaaa || $2d || 3 || 5
|-
| Absolute, X || AND $aaaa,X || $3d || 3 || 5
|-
| Absolute, Y || AND $aaaa,Y || $39 || 3 || 5
|-
| Indirect || AND ($zzzz) || $32 || 3 || 7
|-
| Indexed Indirect || AND ($zz,X) || $21 || 2 || 7
|-
| Indirect, Index || AND ($zz),Y || $31 || 2 || 7
|}

== ASL - Arithmetic Shift Left ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? || ?
|}

<p>Shifts the value at the location specified by the operand left by one bit, shifting in 0 to bit 0, and writes the result back to that location. Bit 7 of the value before the shift is copied to the Carry flag.</p>

{|
|-
| N || Negative Flag || Set if bit 7 of the result is set
|-
| V || Overflow Flag || N/A
|-
| T || T Flag || 0
|-
| D || Decimal Flag || N/A
|-
| I || Interrupt Disable || N/A
|-
| Z || Zero Flag || Set if A == 0
|-
| C || Carry Flag || Set to previous value of bit 7
|-
|}


{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Accumulator || ASL A || $0a || 1 || 2
|-
| Zero Page || ASL $zz || $06 || 2 || 6
|-
| Zero Page, X || ASL $zz,X || $16 || 2 || 6
|-
| Absolute || ASL $aaaa || $0e || 3 || 7
|-
| Absolute, X || ASL $aaaa,X || $1e || 3 || 7
|}

== BBRn - Branch on Bit Reset n ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>If Bit 'n' of the value at the effective address specified by the second operand is clear, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page, Relative || BBR0 $zz, $rr || $0f || 3 || 6*
|-
| Zero Page, Relative || BBR1 $zz, $rr || $1f || 3 || 6*
|-
| Zero Page, Relative || BBR2 $zz, $rr || $2f || 3 || 6*
|-
| Zero Page, Relative || BBR3 $zz, $rr || $3f || 3 || 6*
|-
| Zero Page, Relative || BBR4 $zz, $rr || $4f || 3 || 6*
|-
| Zero Page, Relative || BBR5 $zz, $rr || $5f || 3 || 6*
|-
| Zero Page, Relative || BBR6 $zz, $rr || $6f || 3 || 6*
|-
| Zero Page, Relative || BBR7 $zz, $rr || $7f || 3 || 6*
|}
<pre>* Add 2 extra cycles if branch is taken.</pre>

== BBSn - Branch on Bit Set n ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>If Bit 'n' of the value at the effective address specified by the operand is set, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page, Relative || BBS0 $zz, $rr || $8f || 3 || 6*
|-
| Zero Page, Relative || BBS1 $zz, $rr || $9f || 3 || 6*
|-
| Zero Page, Relative || BBS2 $zz, $rr || $af || 3 || 6*
|-
| Zero Page, Relative || BBS3 $zz, $rr || $bf || 3 || 6*
|-
| Zero Page, Relative || BBS4 $zz, $rr || $cf || 3 || 6*
|-
| Zero Page, Relative || BBS5 $zz, $rr || $df || 3 || 6*
|-
| Zero Page, Relative || BBS6 $zz, $rr || $ef || 3 || 6*
|-
| Zero Page, Relative || BBS7 $zz, $rr || $ff || 3 || 6*
|}
[pre]* Add 2 extra cycles if branch is taken.[/pre]

== BCC - Branch on Carry Clear ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>If the carry flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Relative || BCC $rr || $90 || 2 || 2(4 if branch taken)
|}

== BCS - Branch on Carry Set ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>If the carry flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>

{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Relative || BCS $rr || $b0 || 2 || 2(4 if branch taken)
|}

== BEQ - Branch on Equal(Zero Set) ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>If the zero flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>

{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Relative || BEQ $rr || $f0 || 2 || 2(4 if branch taken)
|}

== BIT - Test Memory Bits with Accumulator ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || ? || 0 || || || ? ||  
|}

<p>Performs an AND between the accumulator and the specified operand without storing the result.
Bit 7 and 6 of the memory operand are respectively saved in the negative (N) and overflow (V) flags. 
</p>

{|
|-
| N || Negative Flag || Bit 7 of M
|-
| V || Overflow Flag || Bit 6 of M
|-
| T || T Flag || 0
|-
| D || Decimal Flag || N/A
|-
| I || Interrupt Disable || N/A
|-
| Z || Zero Flag || Set if A & M == 0
|-
| C || Carry Flag || N/A
|-
|}


{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || BIT #$ii || $89 || 2 || 2
|-
| Zero Page || BIT $zz || $24 || 2 || 4
|-
| Zero Page, X || BIT $zz,X || $34 || 2 || 4
|-
| Absolute || BIT $aaaa || $2c || 3 || 5
|-
| Absolute, X || BIT $aaaa,X || $3c || 3 || 5
|}

== BMI - Branch on Minus(Negative Set) ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>If the negative flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>

{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Relative || BMI $rr || $30 || 2 || 2(4 if branch taken)
|}

== BNE - Branch on Not Equal(Zero Clear) ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>If the zero flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>

{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Relative || BNE $rr || $d0 || 2 || 2(4 if branch taken)
|}

== BPL - Branch on Plus(Negative Clear) ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>If the negative flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>

{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Relative || BPL $rr || $10 || 2 || 2(4 if branch taken)
|}

== BRA - Branch ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Unconditionally branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>

{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Relative || BRA $rr || $80 || 2 || 4
|}

== BRK - Break ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || 0 || 1 || ||  
|}
<p>Forces a software interrupt using [[IRQ2]]'s vector.  Contrary to IRQs, BRK will push the status flags register with bit 4('B' flag) set.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || BRK || $00 || 1 || 8
|}

== BSR - Branch to Subroutine ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}

The program counter (last byte of the BSR instruction) is pushed to stack and the CPU branches to the specified relative address.

{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Relative || BSR $rr || $44 || 2 || 8
|}

== BVC - Branch on Overflow Clear ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>If the overflow flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Relative || BVC $rr || $50 || 2 || 2
|}

== BVS - Branch on Overflow Set ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>If the overflow flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Relative || BVS $rr || $70 || 2 || 2
|}

== CLA - Clear Accumulator ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Clears the accumulator(reset to 0).</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || CLA || $62 || 1 || 2
|}

== CLC - Clear Carry Flag ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || || 0
|}
<p>Clears the carry flag.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || CLC || $18 || 1 || 2
|}

== CLD - Clear Decimal Flag ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || 0 || || ||  
|}
<p>Clears the decimal flag, disabling [[Decimal Mode | decimal mode]].</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || CLD || $d8 || 1 || 2
|}

== CLI - Clear Interrupt Flag ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || 0 || ||  
|}
<p>Clears the interrupt flag, allowing IRQs to be processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || CLI || $58 || 1 || 2
|}

== CLV - Clear Overflow Flag ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || 0 || 0 || || || ||  
|}
Clears the overflow flag (V).
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || CLV || $b8 || 1 || 2
|}

== CLX - Clear X ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
Clears the X register.
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || CLX || $82 || 1 || 2
|}

== CLY - Clear Y ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
Clears the Y register.
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || CLY || $c2 || 1 || 2
|}

== CMP - Compare Accumulator with Memory ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? || ?
|}

The content of the operand is subtracted from the accumulator and the status register is set accordingly. 
The result of the subtraction is not stored.

{|
|-
| N || Negative Flag || Set if bit 7 of the result is set
|-
| V || Overflow Flag || N/A
|-
| T || T Flag || 0
|-
| D || Decimal Flag || N/A
|-
| I || Interrupt Disable || N/A
|-
| Z || Zero Flag || Set if A == M
|-
| C || Carry Flag || Set if A >= M
|-
|}


{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || CMP #$ii || $c9 || 2 || 2
|-
| Zero Page || CMP $zz || $c5 || 2 || 4
|-
| Zero Page, X || CMP $zz,X || $d5 || 2 || 4
|-
| Absolute || CMP $aaaa || $cd || 3 || 5
|-
| Absolute, X || CMP $aaaa,X || $dd || 3 || 5
|-
| Absolute, Y || CMP $aaaa,Y || $d9 || 3 || 5
|-
| Indirect || CMP ($zzzz) || $d2 || 3 || 7
|-
| Indexed Indirect || CMP ($zz,X) || $c1 || 2 || 7
|-
| Indirect, Index || CMP ($zz),Y || $d1 || 2 || 7
|}

== CPX - Compare X with Memory ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? || ?
|}

The content of the operand is subtracted from the X register and the status register is set accordingly. The result of the subtraction is not stored.

{|
|-
| N || Negative Flag || Set if bit 7 of the result is set
|-
| V || Overflow Flag || N/A
|-
| T || T Flag || 0
|-
| D || Decimal Flag || N/A
|-
| I || Interrupt Disable || N/A
|-
| Z || Zero Flag || Set if X == M
|-
| C || Carry Flag || Set if X >= M
|-
|}


{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || CPX #$ii || $e0 || 2 || 2
|-
| Zero Page || CPX $zz || $e4 || 2 || 4
|-
| Absolute || CPX $aaaa || $ec || 3 || 5
|}

== CPY - Compare Y with Memory ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? || ?
|}

The content of the operand is subtracted from the Y register and the status register is set accordingly. The result of the subtraction is not stored.

{|
|-
| N || Negative Flag || Set if bit 7 of the result is set
|-
| V || Overflow Flag || N/A
|-
| T || T Flag || 0
|-
| D || Decimal Flag || N/A
|-
| I || Interrupt Disable || N/A
|-
| Z || Zero Flag || Set if Y == M
|-
| C || Carry Flag || Set if Y >= M
|-
|}


{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || CPY #$ii || $c0 || 2 || 2
|-
| Zero Page || CPY $zz || $c4 || 2 || 4
|-
| Absolute || CPY $aaaa || $cc || 3 || 5
|}

== CSH - Change Speed High ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}

Set CPU to high speed mode (7.16 MHz).

{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || CSH || $d4 || 1 || 3
|}

== CSL - Change Speed Low ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}

Set CPU to low speed mode (1.78 MHz).

{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || CSL || $54 || 1 || 3
|}

== DEC - Decrement ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}

Decrement the operand by 1.

{|
|-
| N || Negative Flag || Set if bit 7 of the result is set
|-
| V || Overflow Flag || N/A
|-
| T || T Flag || 0
|-
| D || Decimal Flag || N/A
|-
| I || Interrupt Disable || N/A
|-
| Z || Zero Flag || Set if the result is zero
|-
| C || Carry Flag || N/A
|-
|}


{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page || DEC $zz || $c6 || 2 || 6
|-
| Zero Page, X || DEC $zz,X || $d6 || 2 || 6
|-
| Absolute || DEC $aaaa || $ce || 3 || 7
|-
| Absolute, X || DEC $aaaa,X || $de || 3 || 7
|}

== DEX - Decrement X ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}

Decrement the X register by 1.

{|
|-
| N || Negative Flag || Set if bit 7 of the X register is set
|-
| V || Overflow Flag || N/A
|-
| T || T Flag || 0
|-
| D || Decimal Flag || N/A
|-
| I || Interrupt Disable || N/A
|-
| Z || Zero Flag || Set if the X register is zero
|-
| C || Carry Flag || N/A
|-
|}


{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || DEX || $ca || 1 || 2
|}

== DEY - Decrement Y ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}

Decrement the Y register by 1.

{|
|-
| N || Negative Flag || Set if bit 7 of the Y register is set
|-
| V || Overflow Flag || N/A
|-
| T || T Flag || 0
|-
| D || Decimal Flag || N/A
|-
| I || Interrupt Disable || N/A
|-
| Z || Zero Flag || Set if the Y register is zero
|-
| C || Carry Flag || N/A
|-
|}


{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || DEY || $88 || 1 || 2
|}

== EOR - Exclusive OR Accumulator with Memory ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Logically [[XOR]] the value referenced by the operand to the accumulator.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || EOR #$ii || $49 || 2 || 2
|-
| Zero Page || EOR $zz || $45 || 2 || 4
|-
| Zero Page, X || EOR $zz,X || $55 || 2 || 4
|-
| Absolute || EOR $aaaa || $4d || 3 || 5
|-
| Absolute, X || EOR $aaaa,X || $5d || 3 || 5
|-
| Absolute, Y || EOR $aaaa,Y || $59 || 3 || 5
|-
| Indirect || EOR ($zzzz) || $52 || 3 || 7
|-
| Indexed Indirect || EOR ($zz,X) || $41 || 2 || 7
|-
| Indirect, Index || EOR ($zz),Y || $51 || 2 || 7
|}

== INC - Increment ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Increments the value of the location specified by the operand by one.  The Carry flag is not used, nor is it modified.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Accumulator || INC A || $1a || 1 || 2
|-
| Zero Page || INC $zz || $e6 || 2 || 6
|-
| Zero Page, X || INC $zz,X || $f6 || 2 || 6
|-
| Absolute || INC $aaaa || $ee || 3 || 7
|-
| Absolute, X || INC $aaaa,X || $fe || 3 || 7
|}

== INX - Increment X ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Increments the value in the X register by one.  The Carry flag is not used, nor is it modified.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || INX || $e8 || 1 || 2
|}

== INY - Increment Y ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Increments the value in the Y register by one.  The Carry flag is not used, nor is it modified.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || INY || $c8 || 1 || 2
|}

== JMP - Jump ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Transfers control(sets the program counter) to the effective address calculated from the operand.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Absolute || JMP $aaaa || $4c || 3 || 4
|-
| Indirect || JMP ($zzzz) || $6c || 3 || 7
|-
| Indexed Indirect || JMP ($zzzz,X) || $7c || 3 || 7
|}

== JSR - Jump to Subroutine ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Absolute || JSR $aaaa || $20 || 3 || 7
|}

== LDA - Load Accumulator ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Loads the accumulator with the value at the effective address.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || LDA #$ii || $a9 || 2 || 2
|-
| Zero Page || LDA $zz || $a5 || 2 || 4
|-
| Zero Page, X || LDA $zz,X || $b5 || 2 || 4
|-
| Absolute || LDA $aaaa || $ad || 3 || 5
|-
| Absolute, X || LDA $aaaa,X || $bd || 3 || 5
|-
| Absolute, Y || LDA $aaaa,Y || $b9 || 3 || 5
|-
| Indirect || LDA ($zzzz) || $b2 || 3 || 7
|-
| Indexed Indirect || LDA ($zz,X) || $a1 || 2 || 7
|-
| Indirect, Index || LDA ($zz),Y || $b1 || 2 || 7
|}

== LDX - Load X ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Loads the X register with the value at the effective address.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || LDX #$ii || $a2 || 2 || 2
|-
| Zero Page || LDX $zz || $a6 || 2 || 4
|-
| Zero Page, Y || LDX $zz,Y || $b6 || 2 || 4
|-
| Absolute || LDX $aaaa || $ae || 3 || 5
|-
| Absolute, Y || LDX $aaaa,Y || $be || 3 || 5
|}

== LDY - Load Y ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Loads the Y register with the value at the effective address.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || LDY #$ii || $a0 || 2 || 2
|-
| Zero Page || LDY $zz || $a4 || 2 || 4
|-
| Zero Page, X || LDY $zz,X || $b4 || 2 || 4
|-
| Absolute || LDY $aaaa || $ac || 3 || 5
|-
| Absolute, X || LDY $aaaa,X || $bc || 3 || 5
|}

== LSR - Logical Shift Right ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? || 0
|}
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Accumulator || LSR A || $4a || 1 || 2
|-
| Zero Page || LSR $zz || $46 || 2 || 6
|-
| Zero Page, X || LSR $zz,X || $56 || 2 || 6
|-
| Absolute || LSR $aaaa || $4e || 3 || 7
|-
| Absolute, X || LSR $aaaa,X || $5e || 3 || 7
|}

== NOP - No Operation ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || NOP || $ea || 1 || 2
|}

== ORA - OR Accumulator with Memory ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Logically [[OR]] the value referenced by the operand with the accumulator, storing the result in the accumulator.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || ORA #$ii || $09 || 2 || 2
|-
| Zero Page || ORA $zz || $05 || 2 || 4
|-
| Zero Page, X || ORA $zz,X || $15 || 2 || 4
|-
| Absolute || ORA $aaaa || $0d || 3 || 5
|-
| Absolute, X || ORA $aaaa,X || $1d || 3 || 5
|-
| Absolute, Y || ORA $aaaa,Y || $19 || 3 || 5
|-
| Indirect || ORA ($zzzz) || $12 || 3 || 7
|-
| Indexed Indirect || ORA ($zz,X) || $01 || 2 || 7
|-
| Indirect, Index || ORA ($zz),Y || $11 || 2 || 7
|}

== PHA - Push A ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Pushes the accumulator to the stack.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || PHA || $48 || 1 || 3
|}

== PHP - Push P ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Pushes the status flags(1 byte) to the stack.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || PHP || $08 || 1 || 3
|}

== PHX - Push X ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Pushes the X register to the stack.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || PHX || $da || 1 || 3
|}

== PHY - Push Y ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Pushes the Y register to the stack.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || PHY || $5a || 1 || 3
|}

== PLA - Pull A ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Pulls a value off the stack, and stores the value in the accumulator.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || PLA || $68 || 1 || 4
|}

== PLP - Pull P ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || ? || ? || ? || ? || ? || ?
|}
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || PLP || $28 || 1 || 4
|}

== PLX - Pull X ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Pulls a value off the stack, and stores the value in the X register.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || PLX || $fa || 1 || 4
|}

== PLY - Pull Y ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Pulls a value off the stack, and stores the value in Y register.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || PLY || $7a || 1 || 4
|}

== RMBn - Reset Memory Bit n ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Reads the zero-page address specified by the operand, resets(clears) the bit "n", and then writes it back to the aforementioned address.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page || RMB0 $zz || $07 || 2 || 7
|-
| Zero Page || RMB1 $zz || $17 || 2 || 7
|-
| Zero Page || RMB2 $zz || $27 || 2 || 7
|-
| Zero Page || RMB3 $zz || $37 || 2 || 7
|-
| Zero Page || RMB4 $zz || $47 || 2 || 7
|-
| Zero Page || RMB5 $zz || $57 || 2 || 7
|-
| Zero Page || RMB6 $zz || $67 || 2 || 7
|-
| Zero Page || RMB7 $zz || $77 || 2 || 7
|}

== ROL - Rotate Left ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? || ?
|}
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Accumulator || ROL A || $2a || 1 || 2
|-
| Zero Page || ROL $zz || $26 || 2 || 6
|-
| Zero Page, X || ROL $zz,X || $36 || 2 || 6
|-
| Absolute || ROL $aaaa || $2e || 3 || 7
|-
| Absolute, X || ROL $aaaa,X || $3e || 3 || 7
|}

== ROR - Rotate Right ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? || ?
|}
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Accumulator || ROR A || $6a || 1 || 2
|-
| Zero Page || ROR $zz || $66 || 2 || 6
|-
| Zero Page, X || ROR $zz,X || $76 || 2 || 6
|-
| Absolute || ROR $aaaa || $6e || 3 || 7
|-
| Absolute, X || ROR $aaaa,X || $7e || 3 || 7
|}

== RTI - Return from Interrupt ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || ? || ? || ? || ? || ? || ?
|}
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || RTI || $40 || 1 || 7
|}

== RTS - Return from Subroutine ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || RTS || $60 || 1 || 7
|}

== SAX - Swap A and X ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Swaps the values in the accumulator and X register.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || SAX || $22 || 1 || 3
|}

== SAY - Swap A and Y ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Swap the values in the accumulator and Y register.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || SAY || $42 || 1 || 3
|}

== SBC - Subtract with Borrow ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || ? || 0 || || || ? || ?
|}
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).</p>
<p>The overflow flag is not affected by this instruction if in Decimal mode.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || SBC #$ii || $e9 || 2 || 2
|-
| Zero Page || SBC $zz || $e5 || 2 || 4
|-
| Zero Page, X || SBC $zz,X || $f5 || 2 || 4
|-
| Absolute || SBC $aaaa || $ed || 3 || 5
|-
| Absolute, X || SBC $aaaa,X || $fd || 3 || 5
|-
| Absolute, Y || SBC $aaaa,Y || $f9 || 3 || 5
|-
| Indirect || SBC ($zzzz) || $f2 || 3 || 7
|-
| Indexed Indirect || SBC ($zz,X) || $e1 || 2 || 7
|-
| Indirect, Index || SBC ($zz),Y || $f1 || 2 || 7
|}

== SEC - Set Carry Flag ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || || 1
|}
<p>Sets the carry flag.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || SEC || $38 || 1 || 2
|}

== SED - Set Decimal Flag ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || 1 || || ||  
|}
<p>Sets the decimal flag, enabling [[Decimal Mode | decimal mode]].</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || SED || $f8 || 1 || 2
|}

== SEI - Set Interrupt Flag ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || 1 || ||  
|}
<p>Sets the interrupt flag, preventing IRQs from being processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || SEI || $78 || 1 || 2
|}

== SET - Set T Flag ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 1 || || || ||  
|}
<p>Sets the T flag, which changes the behavior of the next instruction if the next instruction is ADC, AND, EOR, ORA, or SBC, in which case the operation is performed on the zero-page address specified by the X register, instead of the accumulator.</p>
<p>Note that interrupt processing preserves the T-flag, and clears the T-flag in the interrupt handler, so a programmer needn't worry about an interrupt
occuring between SET and the next instruction.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || SET || $f4 || 1 || 2
|}

== SMBn - Set Memory Bit n ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Reads the zero-page address specified by the operand, sets the bit "n", and then writes it back to the aforementioned address.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page || SMB0 $zz || $87 || 2 || 7
|-
| Zero Page || SMB1 $zz || $97 || 2 || 7
|-
| Zero Page || SMB2 $zz || $a7 || 2 || 7
|-
| Zero Page || SMB3 $zz || $b7 || 2 || 7
|-
| Zero Page || SMB4 $zz || $c7 || 2 || 7
|-
| Zero Page || SMB5 $zz || $d7 || 2 || 7
|-
| Zero Page || SMB6 $zz || $e7 || 2 || 7
|-
| Zero Page || SMB7 $zz || $f7 || 2 || 7
|}

== ST0 - Store [[HuC6270 | (HuC6270) VDC]] No. 0 ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Writes the immediate value to the physical address $1FE000, the [[HuC6270 | (HuC6270) VDC]]'s address register.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || ST0 #$ii || $03 || 2 || 5
|}

== ST1 - Store [[HuC6270 | (HuC6270) VDC]] No. 1 ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Writes the immediate value to the physical address $1FE002, the [[HuC6270 | (HuC6270) VDC]]'s lower data register.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || ST1 #$ii || $13 || 2 || 5
|}

== ST2 - Store [[HuC6270 | (HuC6270) VDC]] No. 2 ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Writes the immediate value to the physical address $1FE003, the [[HuC6270 | (HuC6270) VDC]]'s upper data register.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || ST2 #$ii || $23 || 2 || 5
|}

== STA - Store Accumulator ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Stores the value in the accumulator to the effective address specified by the operand.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page || STA $zz || $85 || 2 || 4
|-
| Zero Page, X || STA $zz,X || $95 || 2 || 4
|-
| Absolute || STA $aaaa || $8d || 3 || 5
|-
| Absolute, X || STA $aaaa,X || $9d || 3 || 5
|-
| Absolute, Y || STA $aaaa,Y || $99 || 3 || 5
|-
| Indirect || STA ($zzzz) || $92 || 3 || 7
|-
| Indexed Indirect || STA ($zz,X) || $81 || 2 || 7
|-
| Indirect, Index || STA ($zz),Y || $91 || 2 || 7
|}

== STX - Store X ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Stores the value in the X register to the effective address specified by the operand.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page || STX $zz || $86 || 2 || 4
|-
| Zero Page, Y || STX $zz,Y || $96 || 2 || 4
|-
| Absolute || STX $aaaa || $8e || 3 || 5
|}

== STY - Store Y ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Stores the value in the Y register to the effective address specified by the operand.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page || STY $zz || $84 || 2 || 4
|-
| Zero Page, X || STY $zz,X || $94 || 2 || 4
|-
| Absolute || STY $aaaa || $8c || 3 || 5
|}

== STZ - Store Zero ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Stores zero to the effective address specified by the operand.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page || STZ $zz || $64 || 2 || 4
|-
| Zero Page, X || STZ $zz,X || $74 || 2 || 4
|-
| Absolute || STZ $aaaa || $9c || 3 || 5
|-
| Absolute, X || STZ $aaaa,X || $9e || 3 || 5
|}

== SXY - Swap X and Y ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Swaps the values in the X register and the Y register.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || SXY || $02 || 1 || 3
|}

== TAI - Transfer Alternate Increment ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
<pre>Alternate = 0
Do
 Value = Read(ssss + Alternate)
 Write(dddd, value)
 dddd = dddd + 1
 llll = llll - 1
 Alternate = Alternate ^ 1
While llll != 0</pre>
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
will be effectively treated as a length of "65536".</p>
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer
is complete.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Block Transfer || TAI $ssss, $dddd, $llll || $f3 || 7 || 17 + 6 * llll
|}

== TAM - Transfer Accumulator to [[MPR | MPRs]] ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Copies the value in the accumulator to each MPR with the corresponding bit set in the immediate operand, eg. TAM #$41 will load MPR0 and MPR6 with the
value in the accumulator.  If no bits are set, no transfer will occur, and the instruction is effectively a 5-cycle NOP.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || TAM #$ii || $53 || 2 || 5
|}

== TAX - Transfer Accumulator to X ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Copies the value of the accumulator to the X register.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || TAX || $aa || 1 || 2
|}

== TAY - Transfer Accumulator to Y ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Copies the value of the accumulator to the Y register.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || TAY || $a8 || 1 || 2
|}

== TDD - Transfer Decrement Decrement ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
<pre>Do
 Value = Read(ssss)
 Write(dddd, value)
 ssss = ssss - 1
 dddd = dddd - 1
 llll = llll - 1
While llll != 0</pre>
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
will be effectively treated as a length of "65536".</p>
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Block Transfer || TDD $ssss, $dddd, $llll || $c3 || 7 || 17 + 6 * llll
|}

== TIA - Transfer Increment Alternate ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p><br />
Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
<pre>Alternate = 0
Do
 Value = Read(ssss)
 Write(dddd + Alternate, Value)
 ssss = ssss + 1
 llll = llll - 1
 Alternate = Alternate ^ 1
While llll != 0</pre>
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
will be effectively treated as a length of "65536".</p>
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Block Transfer || TIA $ssss, $dddd, $llll || $e3 || 7 || 17 + 6 * llll
|}

== TII - Transfer Increment Increment ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
<pre>Do
 Value = Read(ssss)
 Write(dddd, Value)
 ssss = ssss + 1
 dddd = dddd + 1
 llll = llll - 1
While llll != 0</pre>
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
will be effectively treated as a length of "65536".</p>
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Block Transfer || TII $ssss, $dddd, $llll || $73 || 7 || 17 + 6 * llll
|}

== TIN - Transfer Increment ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
<pre>Do
 Value = Read(ssss)
 Write(dddd, value)
 ssss = ssss + 1
 llll = llll - 1
While llll != 0</pre>
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
will be effectively treated as a length of "65536".</p>
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Block Transfer || TIN $ssss, $dddd, $llll || $d3 || 7 || 17 + 6 * llll
|}

== TMA - Transfer MPR to Accumulator ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Copies the value in the MPR, specified by the corresponding bit being set in the immediate operand, to the accumulator.  If an immediate value of $00 is used, the accumulator will be loaded with the last value transfered by TAM(note that if an immediate value of $00 is used with TAM, no transfer occurs, and as such won't be read back if an immediate value of $00 is used with TMA).  Undefined behavior results if multiple bits are set.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate || TMA #$ii || $43 || 2 || 4
|}

== TRB - Test and Reset Bits against Accumulator ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || ? || 0 || || || ? ||  
|}
<p>Loads the value specified by the effective address of the operand, clears all bits whose corresponding bits are set in the accumulator(result = value &amp; ~accumulator), and stores the result to the aforementioned address.</p>
<p>The zero flag is set according to the result.  The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address, before it is operated on.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page || TRB $zz || $14 || 2 || 6
|-
| Absolute || TRB $aaaa || $1c || 3 || 7
|}

== TSB - Test and Set Bits against Accumulator ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || ? || 0 || || || ? ||  
|}
<p>Loads the value specified by the effective address of the operand, sets all bits whose corresponding bits are set in the accumulator(result = value &amp; ~accumulator), and stores the result to the aforementioned address.</p>
<p>The zero flag is set according to the result.  The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address, before it is operated on.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Zero Page || TSB $zz || $04 || 2 || 6
|-
| Absolute || TSB $aaaa || $0c || 3 || 7
|}

== TST - Test ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || ? || 0 || || || ? ||  
|}
<p>The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address(they are *not* set as the result of
the [[AND]] operation used to determine the Z flag's state).</p>
<p>The Z flag is determined according to the result of logically [[AND]]'ing the immediate value and the value at the effective address.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Immediate, Zero Page || TST #$ii, $zz || $83 || 3 || 7
|-
| Immediate, Zero Page, X || TST #$ii, $zz, X || $a3 || 3 || 7
|-
| Immediate, Absolute || TST #$ii, $aaaa || $93 || 4 || 8
|-
| Immediate, Absolute, X || TST #$ii, $aaaa, X || $b3 || 4 || 8
|}

== TSX - Transfer Stack Pointer to X ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || TSX || $ba || 1 || 2
|}

== TXA - Transfer X to A ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Copies the value in the X register to the Accumulator.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || TXA || $8a || 1 || 2
|}

== TXS - Track X to Stack Pointer ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| || || 0 || || || ||  
|}
<p>Copies the value in X to the [[Stack Pointer | stack pointer]].</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || TXS || $9a || 1 || 2
|}

== TYA - Transfer Y to Accumulator ==
{|
|-
! N !! V !! T !! D !! I !! Z !! C
|-
| ? || || 0 || || || ? ||  
|}
<p>Copies the value in Y to the Accumulator.</p>
{| class="addressing"
|-
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
|-
| Implied || TYA || $98 || 1 || 2
|}