Difference between revisions of "HuC6280 Instruction Set"

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== ADC - Add with Carry ==
+
<css>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
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table
 +
{
 +
  border-collapse: collapse;
 +
  spacing:1px;
 +
}
  
<tr style="background: #efefef">
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table th
<td><b>N</b>
+
{
</td><td><b>V</b>
+
  font-family: Courier, monospace;
</td><td><b>T</b>
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  background-color: #dddddd;
</td><td><b>D</b>
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  padding-left:10px;
 +
  padding-right:10px;
 +
  padding-top:2px;
 +
  padding-bottom:2px;
 +
  border-width:1px;
 +
  border-style: solid;
 +
  text-align: center;
 +
}
  
</td><td><b>I</b>
+
table td
</td><td><b>Z</b>
+
{
</td><td><b>C</b>
+
  padding-left:10px;
</td></tr>
+
  padding-right:10px;
<tr>
+
  border-width:1px;
<td>?
+
  border-style: solid;
</td><td>?
+
}
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>?
+
</td></tr></table>
+
<p>Add the value specified by the operand, and 1 if the Carry flag is set, to the value in the accumulator.  If the result is too large to fit in the accumulator, the carry flag will be set, otherwise it will be cleared.
+
  
</p><p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).
+
.addressing { width: 525px; }
</p><p>The overflow flag is not affected by this instruction if in Decimal mode; otherwise, if bit7 of the result&nbsp;!= bit7 of the accumulator before the operation, and bit7 of the accumulator before the operation == bit7 of the value specified by the operand, the overflow flag is set, otherwise it is cleared. In other words, if we were to treat the accumulator and value specified by the operand as <a href="http://en.wikipedia.org/wiki/Two%27s_complement" class='external text' title="http://en.wikipedia.org/wiki/Two%27s_complement" rel="nofollow">two's complement</a> numbers, in the range of -128 to 127, the overflow flag will be set if the end result is outside of this range(otherwise it will be cleared).
+
.addressing td:nth-child(n + 3) { text-align: center; }
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
  
<tr style="background: #efefef">
+
table pre
<td><b>Addressing Mode</b>
+
{
</td><td><b>Syntax</b>
+
  border-style: hidden;
</td><td><b>Opcode</b>
+
  background-color: inherit;
</td><td><b>Bytes</b>
+
}
 +
</css>
 +
== ADC - Add with Carry ==
 +
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || ? || 0 || || || ? || ?
 +
|}
 +
<p>Add the value specified by the operand, and 1 if the Carry flag is set, to the value in the accumulator.  If the result is too large to fit in the accumulator, the carry flag will be set, otherwise it will be cleared.</p>
 +
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).</p>
 +
<p>The overflow flag is not affected by this instruction if in Decimal mode; otherwise, if bit 7 of the result != bit  7 of the accumulator before the operation, and bit 7 of the accumulator before the operation == bit 7 of the value specified by the operand, the overflow flag is set, otherwise it is cleared.  In other words, if we were to treat the accumulator and value specified by the operand as [http://en.wikipedia.org/wiki/Two%27s_complement two's complement] numbers, in the range of -128 to 127, the overflow flag will be set if the end result is outside of this range(otherwise it will be cleared).</p>
 +
<p>If T=1 (the previous instruction is SET) the zero-page byte specified by the X register is used instead of the A register.</p>
  
</td><td><b>Cycles</b>
+
<p>Here is a recap of the status register after use :</p>
</td></tr>
+
{|
<tr>
+
|-
<td>Immediate
+
| N || Negative Flag || Set if bit 7 is set
</td><td>ADC #$ii
+
|-
</td><td>$69
+
| V || Overflow Flag || Set if bit 7 (sign bit for 2's complement number) is incorrect
</td><td>2
+
|-
</td><td>2
+
| T || T Flag || 0
</td></tr>
+
|-
<tr>
+
| D || Decimal Flag || N/A
<td>Zero Page
+
|-
</td><td>ADC $zz
+
| I || Interrupt Disable || N/A
</td><td>$65
+
|-
</td><td>2
+
| Z || Zero Flag || Set if A == 0
</td><td>4
+
|-
</td></tr>
+
| C || Carry Flag || Set if overflow in bit 7 occured
 +
|-
 +
|}
  
<tr>
 
<td>Zero Page, X
 
</td><td>ADC $zz,X
 
</td><td>$75
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>ADC $aaaa
 
</td><td>$6d
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>ADC $aaaa,X
 
  
</td><td>$7d
+
{| class="addressing"
</td><td>3
+
|-
</td><td>5
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td></tr>
+
|-
<tr>
+
| Immediate || ADC #$ii || $69 || 2 || 2
<td>Absolute, Y
+
|-
</td><td>ADC $aaaa,Y
+
| Zero Page || ADC $zz || $65 || 2 || 4
</td><td>$79
+
|-
</td><td>3
+
| Zero Page, X || ADC $zz,X || $75 || 2 || 4
</td><td>5
+
|-
</td></tr>
+
| Absolute || ADC $aaaa || $6d || 3 || 5
<tr>
+
|-
<td>Indirect
+
| Absolute, X || ADC $aaaa,X || $7d || 3 || 5
</td><td>ADC ($zz)
+
|-
</td><td>$72
+
| Absolute, Y || ADC $aaaa,Y || $79 || 3 || 5
</td><td>3
+
|-
</td><td>7
+
| Indirect || ADC ($zzzz) || $72 || 3 || 7
 +
|-
 +
| Indexed Indirect || ADC ($zz,X) || $61 || 2 || 7
 +
|-
 +
| Indirect, Index || ADC ($zz),Y || $71 || 2 || 7
 +
|}
  
</td></tr>
 
<tr>
 
<td>Indexed Indirect
 
</td><td>ADC ($zz,X)
 
</td><td>$61
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indirect, Index
 
</td><td>ADC ($zz),Y
 
</td><td>$71
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== AND - AND Accumulator with Memory ==
 
== AND - AND Accumulator with Memory ==
 +
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
  
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
Performs a bit by bit logical and on the accumulator with the value specified by the operand.
  
<tr style="background: #efefef">
+
<p>Here is a recap of the processor status flags after use :</p>
<td><b>N</b>
+
{|
</td><td><b>V</b>
+
|-
</td><td><b>T</b>
+
| N || Negative Flag || Set if bit 7 is set
</td><td><b>D</b>
+
|-
</td><td><b>I</b>
+
| V || Overflow Flag || N/A
</td><td><b>Z</b>
+
|-
</td><td><b>C</b>
+
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if A == 0
 +
|-
 +
| C || Carry Flag || N/A
 +
|-
 +
|}
  
</td></tr>
 
<tr>
 
<td>?
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>
 
</td></tr></table>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
  
<tr style="background: #efefef">
+
{| class="addressing"
<td><b>Addressing Mode</b>
+
|-
</td><td><b>Syntax</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Immediate || AND #$ii || $29 || 2 || 2
 +
|-
 +
| Zero Page || AND $zz || $25 || 2 || 4
 +
|-
 +
| Zero Page, X || AND $zz,X || $35 || 2 || 4
 +
|-
 +
| Absolute || AND $aaaa || $2d || 3 || 5
 +
|-
 +
| Absolute, X || AND $aaaa,X || $3d || 3 || 5
 +
|-
 +
| Absolute, Y || AND $aaaa,Y || $39 || 3 || 5
 +
|-
 +
| Indirect || AND ($zzzz) || $32 || 3 || 7
 +
|-
 +
| Indexed Indirect || AND ($zz,X) || $21 || 2 || 7
 +
|-
 +
| Indirect, Index || AND ($zz),Y || $31 || 2 || 7
 +
|}
  
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
</td><td>AND #$ii
 
</td><td>$29
 
</td><td>2
 
</td><td>2
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>AND $zz
 
 
</td><td>$25
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Zero Page, X
 
</td><td>AND $zz,X
 
</td><td>$35
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>AND $aaaa
 
</td><td>$2d
 
</td><td>3
 
</td><td>5
 
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>AND $aaaa,X
 
</td><td>$3d
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, Y
 
</td><td>AND $aaaa,Y
 
</td><td>$39
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Indirect
 
 
</td><td>AND ($zz)
 
</td><td>$32
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indexed Indirect
 
</td><td>AND ($zz,X)
 
</td><td>$21
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indirect, Index
 
</td><td>AND ($zz),Y
 
</td><td>$31
 
</td><td>2
 
 
</td><td>7
 
</td></tr>
 
</table>
 
<p><br />
 
</p>
 
 
== ASL - Arithmetic Shift Left ==
 
== ASL - Arithmetic Shift Left ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || ?
 +
|}
  
<tr style="background: #efefef">
+
<p>Shifts the value at the location specified by the operand left by one bit, shifting in 0 to bit 0, and writes the result back to that location. Bit 7 of the value before the shift is copied to the Carry flag.</p>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
  
</td><td><b>D</b>
+
{|
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
| N || Negative Flag || Set if bit 7 of the result is set
</td><td><b>C</b>
+
|-
</td></tr>
+
| V || Overflow Flag || N/A
<tr>
+
|-
<td>?
+
| T || T Flag || 0
</td><td>
+
|-
</td><td>0
+
| D || Decimal Flag || N/A
</td><td>
+
|-
</td><td>
+
| I || Interrupt Disable || N/A
</td><td>?
+
|-
</td><td>?
+
| Z || Zero Flag || Set if A == 0
 +
|-
 +
| C || Carry Flag || Set to previous value of bit 7
 +
|-
 +
|}
  
</td></tr></table>
 
<p>Shifts the value at the location specified by the operand left by one bit, shifting in 0 to Bit0, and writes the result back to that location.  Bit7 of the value before the shift is copied to the Carry flag.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
 
<tr>
 
<td>Accumulator
 
</td><td>ASL A
 
</td><td>$0a
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>ASL $zz
 
</td><td>$06
 
</td><td>2
 
</td><td>6
 
</td></tr>
 
<tr>
 
<td>Zero Page, X
 
</td><td>ASL $zz,X
 
  
</td><td>$16
+
{| class="addressing"
</td><td>2
+
|-
</td><td>6
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td></tr>
+
|-
<tr>
+
| Accumulator || ASL A || $0a || 1 || 2
<td>Absolute
+
|-
</td><td>ASL $aaaa
+
| Zero Page || ASL $zz || $06 || 2 || 6
</td><td>$0e
+
|-
</td><td>3
+
| Zero Page, X || ASL $zz,X || $16 || 2 || 6
</td><td>7
+
|-
</td></tr>
+
| Absolute || ASL $aaaa || $0e || 3 || 7
<tr>
+
|-
<td>Absolute, X
+
| Absolute, X || ASL $aaaa,X || $1e || 3 || 7
</td><td>ASL $aaaa,X
+
|}
</td><td>$1e
+
</td><td>3
+
</td><td>7
+
  
</td></tr>
 
</table>
 
 
== BBRn - Branch on Bit Reset n ==
 
== BBRn - Branch on Bit Reset n ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If Bit 'n' of the value at the effective address specified by the second operand is clear, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If Bit 'n' of the value at the effective address specified by the second operand is clear, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p>
+
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Zero Page, Relative || BBR0 $zz, $rr || $0f || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBR1 $zz, $rr || $1f || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBR2 $zz, $rr || $2f || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBR3 $zz, $rr || $3f || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBR4 $zz, $rr || $4f || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBR5 $zz, $rr || $5f || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBR6 $zz, $rr || $6f || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBR7 $zz, $rr || $7f || 3 || 6*
 +
|}
 +
<pre>* Add 2 extra cycles if branch is taken.</pre>
  
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBR0 $zz, $rrrr
 
 
</td><td>$0f
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBR1 $zz, $rrrr
 
</td><td>$1f
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBR2 $zz, $rrrr
 
</td><td>$2f
 
</td><td>3
 
</td><td>6*
 
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBR3 $zz, $rrrr
 
</td><td>$3f
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBR4 $zz, $rrrr
 
</td><td>$4f
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
 
</td><td>BBR5 $zz, $rrrr
 
</td><td>$5f
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBR6 $zz, $rrrr
 
</td><td>$6f
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBR7 $zz, $rrrr
 
</td><td>$7f
 
</td><td>3
 
 
</td><td>6*
 
</td></tr>
 
</table>
 
<pre>* Add 2 extra cycles if branch is taken.
 
</pre>
 
 
== BBSn - Branch on Bit Set n ==
 
== BBSn - Branch on Bit Set n ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
 
+
</td></tr></table>
+
 
<p>If Bit 'n' of the value at the effective address specified by the operand is set, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If Bit 'n' of the value at the effective address specified by the operand is set, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p>
+
{| class="addressing"
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Zero Page, Relative || BBS0 $zz, $rr || $8f || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBS1 $zz, $rr || $9f || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBS2 $zz, $rr || $af || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBS3 $zz, $rr || $bf || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBS4 $zz, $rr || $cf || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBS5 $zz, $rr || $df || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBS6 $zz, $rr || $ef || 3 || 6*
 +
|-
 +
| Zero Page, Relative || BBS7 $zz, $rr || $ff || 3 || 6*
 +
|}
 +
[pre]* Add 2 extra cycles if branch is taken.[/pre]
  
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBS0 $zz, $rrrr
 
</td><td>$8f
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBS1 $zz, $rrrr
 
</td><td>$9f
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
 
</td><td>BBS2 $zz, $rrrr
 
</td><td>$af
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBS3 $zz, $rrrr
 
</td><td>$bf
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBS4 $zz, $rrrr
 
</td><td>$cf
 
</td><td>3
 
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBS5 $zz, $rrrr
 
</td><td>$df
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
<td>Zero Page, Relative
 
</td><td>BBS6 $zz, $rrrr
 
</td><td>$ef
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
<tr>
 
 
<td>Zero Page, Relative
 
</td><td>BBS7 $zz, $rrrr
 
</td><td>$ff
 
</td><td>3
 
</td><td>6*
 
</td></tr>
 
</table>
 
<pre>* Add 2 extra cycles if branch is taken.
 
</pre>
 
 
== BCC - Branch on Carry Clear ==
 
== BCC - Branch on Carry Clear ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
 
+
| || || 0 || || || || 
</td><td><b>V</b>
+
|}
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
 
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the carry flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the carry flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p>
+
{| class="addressing"
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
<tr style="background: #efefef">
+
|-
<td><b>Addressing Mode</b>
+
| Relative || BCC $rr || $90 || 2 || 2(4 if branch taken)
</td><td><b>Syntax</b>
+
|}
</td><td><b>Opcode</b>
+
  
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Relative
 
</td><td>BCC $rrrr
 
</td><td>$90
 
</td><td>2
 
</td><td>2(4 if branch taken)
 
</td></tr>
 
</table>
 
 
== BCS - Branch on Carry Set ==
 
== BCS - Branch on Carry Set ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the carry flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the carry flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
  
<tr style="background: #efefef">
+
{| class="addressing"
<td><b>Addressing Mode</b>
+
|-
 
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>Syntax</b>
+
|-
</td><td><b>Opcode</b>
+
| Relative || BCS $rr || $b0 || 2 || 2(4 if branch taken)
</td><td><b>Bytes</b>
+
|}
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BCS $rrrr
+
</td><td>$b0
+
</td><td>2
+
</td><td>2(4 if branch taken)
+
</td></tr>
+
</table>
+
  
 
== BEQ - Branch on Equal(Zero Set) ==
 
== BEQ - Branch on Equal(Zero Set) ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the zero flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the zero flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
  
<tr style="background: #efefef">
+
{| class="addressing"
<td><b>Addressing Mode</b>
+
|-
</td><td><b>Syntax</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>Opcode</b>
+
|-
</td><td><b>Bytes</b>
+
| Relative || BEQ $rr || $f0 || 2 || 2(4 if branch taken)
</td><td><b>Cycles</b>
+
|}
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BEQ $rrrr
+
</td><td>$f0
+
  
</td><td>2
 
</td><td>2(4 if branch taken)
 
</td></tr>
 
</table>
 
 
== BIT - Test Memory Bits with Accumulator ==
 
== BIT - Test Memory Bits with Accumulator ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || ? || 0 || || || ? || 
 +
|}
  
<tr style="background: #efefef">
+
<p>Performs an AND between the accumulator and the specified operand without storing the result.
<td><b>N</b>
+
Bit 7 and 6 of the memory operand are respectively saved in the negative (N) and overflow (V) flags.
</td><td><b>V</b>
+
</p>
</td><td><b>T</b>
+
</td><td><b>D</b>
+
  
</td><td><b>I</b>
+
{|
</td><td><b>Z</b>
+
|-
</td><td><b>C</b>
+
| N || Negative Flag || Bit 7 of M
</td></tr>
+
|-
<tr>
+
| V || Overflow Flag || Bit 6 of M
<td>?
+
|-
</td><td>?
+
| T || T Flag || 0
</td><td>0
+
|-
</td><td>
+
| D || Decimal Flag || N/A
</td><td>
+
|-
</td><td>?
+
| I || Interrupt Disable || N/A
</td><td>
+
|-
</td></tr></table>
+
| Z || Zero Flag || Set if A & M == 0
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 +
| C || Carry Flag || N/A
 +
|-
 +
|}
  
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
</td><td>BIT #$ii
 
</td><td>$89
 
  
</td><td>2
+
{| class="addressing"
</td><td>2
+
|-
</td></tr>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
<tr>
+
|-
<td>Zero Page
+
| Immediate || BIT #$ii || $89 || 2 || 2
</td><td>BIT $zz
+
|-
</td><td>$24
+
| Zero Page || BIT $zz || $24 || 2 || 4
</td><td>2
+
|-
</td><td>4
+
| Zero Page, X || BIT $zz,X || $34 || 2 || 4
</td></tr>
+
|-
<tr>
+
| Absolute || BIT $aaaa || $2c || 3 || 5
<td>Zero Page, X
+
|-
</td><td>BIT $zz,X
+
| Absolute, X || BIT $aaaa,X || $3c || 3 || 5
</td><td>$34
+
|}
</td><td>2
+
</td><td>4
+
</td></tr>
+
  
<tr>
 
<td>Absolute
 
</td><td>BIT $aaaa
 
</td><td>$2c
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>BIT $aaaa,X
 
</td><td>$3c
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
</table>
 
 
== BMI - Branch on Minus(Negative Set) ==
 
== BMI - Branch on Minus(Negative Set) ==
 
+
{|
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 
+
! N !! V !! T !! D !! I !! Z !! C
<tr style="background: #efefef">
+
|-
<td><b>N</b>
+
| || || 0 || || || || 
</td><td><b>V</b>
+
|}
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the negative flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the negative flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
  
<tr style="background: #efefef">
+
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Relative || BMI $rr || $30 || 2 || 2(4 if branch taken)
 +
|}
  
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Relative
 
</td><td>BMI $rrrr
 
</td><td>$30
 
</td><td>2
 
</td><td>2(4 if branch taken)
 
 
</td></tr>
 
</table>
 
 
== BNE - Branch on Not Equal(Zero Clear) ==
 
== BNE - Branch on Not Equal(Zero Clear) ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the zero flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the zero flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
  
</p>
+
{| class="addressing"
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Relative || BNE $rr || $d0 || 2 || 2(4 if branch taken)
 +
|}
  
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Relative
 
 
</td><td>BNE $rrrr
 
</td><td>$d0
 
</td><td>2
 
</td><td>2(4 if branch taken)
 
</td></tr>
 
</table>
 
 
== BPL - Branch on Plus(Negative Clear) ==
 
== BPL - Branch on Plus(Negative Clear) ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
 
+
</td></tr></table>
+
 
<p>If the negative flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the negative flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
  
<tr style="background: #efefef">
+
{| class="addressing"
<td><b>Addressing Mode</b>
+
|-
</td><td><b>Syntax</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>Opcode</b>
+
|-
</td><td><b>Bytes</b>
+
| Relative || BPL $rr || $10 || 2 || 2(4 if branch taken)
</td><td><b>Cycles</b>
+
|}
  
</td></tr>
 
<tr>
 
<td>Relative
 
</td><td>BPL $rrrr
 
</td><td>$10
 
</td><td>2
 
</td><td>2(4 if branch taken)
 
</td></tr>
 
</table>
 
 
== BRA - Branch ==
 
== BRA - Branch ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
 
+
| || || 0 || || || || 
</td><td><b>V</b>
+
|}
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
 
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>Unconditionally branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>Unconditionally branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
  
<tr style="background: #efefef">
+
{| class="addressing"
<td><b>Addressing Mode</b>
+
|-
</td><td><b>Syntax</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>Opcode</b>
+
|-
 +
| Relative || BRA $rr || $80 || 2 || 4
 +
|}
  
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Relative
 
</td><td>BRA $rrrr
 
</td><td>$80
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
</table>
 
 
== BRK - Break ==
 
== BRK - Break ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || 0 || 1 || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
<p>Forces a software interrupt using [[IRQ2]]'s vector.  Contrary to IRQs, BRK will push the status flags register with bit 4('B' flag) set.</p>
</td><td><b>I</b>
+
{| class="addressing"
</td><td><b>Z</b>
+
|-
</td><td><b>C</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td></tr>
+
|-
 
+
| Implied || BRK || $00 || 1 || 8
<tr>
+
|}
<td>
+
</td><td>
+
</td><td>0
+
</td><td>0
+
</td><td>1
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Forces a software interrupt using <a href="/index.php?title=IRQ2&amp;action=edit" class="new" title="IRQ2">IRQ2</a>'s vector.  Contrary to IRQs, BRK will push the status flags register with bit 4('B' flag) set.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>BRK
+
</td><td>$00
+
</td><td>1
+
</td><td>8
+
</td></tr>
+
</table>
+
  
 
== BSR - Branch to Subroutine ==
 
== BSR - Branch to Subroutine ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
  
<tr style="background: #efefef">
+
The program counter (last byte of the BSR instruction) is pushed to stack and the CPU branches to the specified relative address.
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
  
</td><td><b>C</b>
+
{| class="addressing"
</td></tr>
+
|-
<tr>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
<td>
+
|-
</td><td>
+
| Relative || BSR $rr || $44 || 2 || 8
</td><td>0
+
|}
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BSR $rrrr
+
</td><td>$44
+
</td><td>2
+
</td><td>8
+
</td></tr>
+
</table>
+
  
 
== BVC - Branch on Overflow Clear ==
 
== BVC - Branch on Overflow Clear ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the overflow flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the overflow flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p>
+
{| class="addressing"
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
<tr style="background: #efefef">
+
|-
<td><b>Addressing Mode</b>
+
| Relative || BVC $rr || $50 || 2 || 2
</td><td><b>Syntax</b>
+
|}
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BVC $rrrr
+
</td><td>$50
+
</td><td>2
+
  
</td><td>2
 
</td></tr>
 
</table>
 
 
== BVS - Branch on Overflow Set ==
 
== BVS - Branch on Overflow Set ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
 
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the overflow flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the overflow flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
{| class="addressing"
</p>
+
|-
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
+
|-
<tr style="background: #efefef">
+
| Relative || BVS $rr || $70 || 2 || 2
<td><b>Addressing Mode</b>
+
|}
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
  
<td>Relative
 
</td><td>BVS $rrrr
 
</td><td>$70
 
</td><td>2
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== CLA - Clear Accumulator ==
 
== CLA - Clear Accumulator ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
 +
<p>Clears the accumulator(reset to 0).</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || CLA || $62 || 1 || 2
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<p>Clears the accumulator(reset to 0).
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>CLA
 
</td><td>$62
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== CLC - Clear Carry Flag ==
 
== CLC - Clear Carry Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 0
 +
|}
 +
<p>Clears the carry flag.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || CLC || $18 || 1 || 2
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
 
</td><td>
 
</td><td>
 
</td><td>
 
</td><td>0
 
</td></tr></table>
 
<p>Clears the carry flag.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>CLC
 
</td><td>$18
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== CLD - Clear Decimal Flag ==
 
== CLD - Clear Decimal Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
 
+
|-
<td><b>N</b>
+
| || || 0 || 0 || || || 
</td><td><b>V</b>
+
|}
</td><td><b>T</b>
+
<p>Clears the decimal flag, disabling [[Decimal Mode | decimal mode]].</p>
</td><td><b>D</b>
+
{| class="addressing"
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Implied || CLD || $d8 || 1 || 2
<tr>
+
|}
<td>
+
 
+
</td><td>
+
</td><td>0
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Clears the decimal flag, disabling <a href="/index.php?title=decimal_mode&amp;action=edit" class="new" title="decimal_mode">decimal mode</a>.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
  
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>CLD
 
</td><td>$d8
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== CLI - Clear Interrupt Flag ==
 
== CLI - Clear Interrupt Flag ==
 
+
{|
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 
+
! N !! V !! T !! D !! I !! Z !! C
<tr style="background: #efefef">
+
|-
<td><b>N</b>
+
| || || 0 || || 0 || || 
</td><td><b>V</b>
+
|}
</td><td><b>T</b>
+
<p>Clears the interrupt flag, allowing IRQs to be processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).</p>
</td><td><b>D</b>
+
{| class="addressing"
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
 
+
| Implied || CLI || $58 || 1 || 2
</td></tr>
+
|}
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Clears the interrupt flag, allowing IRQs to be processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLI
+
</td><td>$58
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
  
 
== CLV - Clear Overflow Flag ==
 
== CLV - Clear Overflow Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || 0 || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
Clears the overflow flag (V).
</td><td><b>I</b>
+
{| class="addressing"
</td><td><b>Z</b>
+
|-
 
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Implied || CLV || $b8 || 1 || 2
<tr>
+
|}
<td>
+
</td><td>0
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLV
+
</td><td>$b8
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
  
 
== CLX - Clear X ==
 
== CLX - Clear X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
Clears the X register.
</td><td><b>I</b>
+
{| class="addressing"
</td><td><b>Z</b>
+
|-
 
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Implied || CLX || $82 || 1 || 2
<tr>
+
|}
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLX
+
</td><td>$82
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
  
 
== CLY - Clear Y ==
 
== CLY - Clear Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
Clears the Y register.
</td><td><b>I</b>
+
{| class="addressing"
</td><td><b>Z</b>
+
|-
 
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Implied || CLY || $c2 || 1 || 2
<tr>
+
|}
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLY
+
</td><td>$c2
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
  
 
== CMP - Compare Accumulator with Memory ==
 
== CMP - Compare Accumulator with Memory ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || ?
 +
|}
  
<tr style="background: #efefef">
+
The content of the operand is subtracted from the accumulator and the status register is set accordingly.
<td><b>N</b>
+
The result of the subtraction is not stored.
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
  
</td><td><b>C</b>
+
{|
</td></tr>
+
|-
<tr>
+
| N || Negative Flag || Set if bit 7 of the result is set
<td>?
+
|-
</td><td>
+
| V || Overflow Flag || N/A
</td><td>0
+
|-
</td><td>
+
| T || T Flag || 0
</td><td>
+
|-
</td><td>?
+
| D || Decimal Flag || N/A
</td><td>?
+
|-
</td></tr></table>
+
| I || Interrupt Disable || N/A
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 +
| Z || Zero Flag || Set if A == M
 +
|-
 +
| C || Carry Flag || Set if A >= M
 +
|-
 +
|}
  
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
  
</td><td><b>Syntax</b>
+
{| class="addressing"
</td><td><b>Opcode</b>
+
|-
</td><td><b>Bytes</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>Cycles</b>
+
|-
</td></tr>
+
| Immediate || CMP #$ii || $c9 || 2 || 2
<tr>
+
|-
<td>Immediate
+
| Zero Page || CMP $zz || $c5 || 2 || 4
</td><td>CMP #$ii
+
|-
</td><td>$c9
+
| Zero Page, X || CMP $zz,X || $d5 || 2 || 4
</td><td>2
+
|-
</td><td>2
+
| Absolute || CMP $aaaa || $cd || 3 || 5
</td></tr>
+
|-
<tr>
+
| Absolute, X || CMP $aaaa,X || $dd || 3 || 5
 +
|-
 +
| Absolute, Y || CMP $aaaa,Y || $d9 || 3 || 5
 +
|-
 +
| Indirect || CMP ($zzzz) || $d2 || 3 || 7
 +
|-
 +
| Indexed Indirect || CMP ($zz,X) || $c1 || 2 || 7
 +
|-
 +
| Indirect, Index || CMP ($zz),Y || $d1 || 2 || 7
 +
|}
  
<td>Zero Page
 
</td><td>CMP $zz
 
</td><td>$c5
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Zero Page, X
 
</td><td>CMP $zz,X
 
</td><td>$d5
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>CMP $aaaa
 
</td><td>$cd
 
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>CMP $aaaa,X
 
</td><td>$dd
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, Y
 
</td><td>CMP $aaaa,Y
 
</td><td>$d9
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
 
<tr>
 
<td>Indirect
 
</td><td>CMP ($zz)
 
</td><td>$d2
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indexed Indirect
 
</td><td>CMP ($zz,X)
 
</td><td>$c1
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indirect, Index
 
</td><td>CMP ($zz),Y
 
 
</td><td>$d1
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== CPX - Compare X with Memory ==
 
== CPX - Compare X with Memory ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| ? || || 0 || || || ? || ?
</td><td><b>T</b>
+
|}
  
</td><td><b>D</b>
+
The content of the operand is subtracted from the X register and the status register is set accordingly. The result of the subtraction is not stored.
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>?
+
  
</td></tr></table>
+
{|
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 +
| N || Negative Flag || Set if bit 7 of the result is set
 +
|-
 +
| V || Overflow Flag || N/A
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if X == M
 +
|-
 +
| C || Carry Flag || Set if X >= M
 +
|-
 +
|}
  
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
  
</td><td>CPX #$ii
+
{| class="addressing"
</td><td>$e0
+
|-
</td><td>2
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td>2
+
|-
</td></tr>
+
| Immediate || CPX #$ii || $e0 || 2 || 2
<tr>
+
|-
<td>Zero Page
+
| Zero Page || CPX $zz || $e4 || 2 || 4
</td><td>CPX $zz
+
|-
</td><td>$e4
+
| Absolute || CPX $aaaa || $ec || 3 || 5
</td><td>2
+
|}
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>CPX $aaaa
+
</td><td>$ec
+
</td><td>3
+
  
</td><td>5
 
</td></tr>
 
</table>
 
 
== CPY - Compare Y with Memory ==
 
== CPY - Compare Y with Memory ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || ?
 +
|}
  
<tr style="background: #efefef">
+
The content of the operand is subtracted from the Y register and the status register is set accordingly. The result of the subtraction is not stored.
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
  
</td><td><b>I</b>
+
{|
</td><td><b>Z</b>
+
|-
</td><td><b>C</b>
+
| N || Negative Flag || Set if bit 7 of the result is set
</td></tr>
+
|-
<tr>
+
| V || Overflow Flag || N/A
<td>?
+
|-
</td><td>
+
| T || T Flag || 0
</td><td>0
+
|-
</td><td>
+
| D || Decimal Flag || N/A
</td><td>
+
|-
</td><td>?
+
| I || Interrupt Disable || N/A
</td><td>?
+
|-
</td></tr></table>
+
| Z || Zero Flag || Set if Y == M
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 +
| C || Carry Flag || Set if Y >= M
 +
|-
 +
|}
  
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
</td><td>CPY #$ii
 
</td><td>$c0
 
  
</td><td>2
+
{| class="addressing"
</td><td>2
+
|-
</td></tr>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
<tr>
+
|-
<td>Zero Page
+
| Immediate || CPY #$ii || $c0 || 2 || 2
</td><td>CPY $zz
+
|-
</td><td>$c4
+
| Zero Page || CPY $zz || $c4 || 2 || 4
</td><td>2
+
|-
</td><td>4
+
| Absolute || CPY $aaaa || $cc || 3 || 5
</td></tr>
+
|}
<tr>
+
<td>Absolute
+
</td><td>CPY $aaaa
+
</td><td>$cc
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
  
</table>
 
 
== CSH - Change Speed High ==
 
== CSH - Change Speed High ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
  
<tr style="background: #efefef">
+
Set CPU to high speed mode (7.16 MHz).
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
  
</td><td><b>Z</b>
+
{| class="addressing"
</td><td><b>C</b>
+
|-
</td></tr>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
<tr>
+
|-
<td>
+
| Implied || CSH || $d4 || 1 || 3
</td><td>
+
|}
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
  
<tr style="background: #efefef">
 
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>CSH
 
</td><td>$d4
 
</td><td>1
 
</td><td>3
 
 
</td></tr>
 
</table>
 
 
== CSL - Change Speed Low ==
 
== CSL - Change Speed Low ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
  
<tr style="background: #efefef">
+
Set CPU to low speed mode (1.78 MHz).
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
  
</td><td><b>Z</b>
+
{| class="addressing"
</td><td><b>C</b>
+
|-
</td></tr>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
<tr>
+
|-
<td>
+
| Implied || CSL || $54 || 1 || 3
</td><td>
+
|}
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
  
<tr style="background: #efefef">
 
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>CSL
 
</td><td>$54
 
</td><td>1
 
</td><td>3
 
 
</td></tr>
 
</table>
 
 
== DEC - Decrement ==
 
== DEC - Decrement ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
  
<tr style="background: #efefef">
+
Decrement the operand by 1.
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
  
</td><td><b>Z</b>
+
{|
</td><td><b>C</b>
+
|-
</td></tr>
+
| N || Negative Flag || Set if bit 7 of the result is set
<tr>
+
|-
<td>?
+
| V || Overflow Flag || N/A
</td><td>
+
|-
</td><td>0
+
| T || T Flag || 0
</td><td>
+
|-
</td><td>
+
| D || Decimal Flag || N/A
</td><td>?
+
|-
</td><td>
+
| I || Interrupt Disable || N/A
</td></tr></table>
+
|-
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
| Z || Zero Flag || Set if the result is zero
 +
|-
 +
| C || Carry Flag || N/A
 +
|-
 +
|}
  
<tr style="background: #efefef">
 
  
<td><b>Addressing Mode</b>
+
{| class="addressing"
</td><td><b>Syntax</b>
+
|-
</td><td><b>Opcode</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>Bytes</b>
+
|-
</td><td><b>Cycles</b>
+
| Zero Page || DEC $zz || $c6 || 2 || 6
</td></tr>
+
|-
<tr>
+
| Zero Page, X || DEC $zz,X || $d6 || 2 || 6
<td>Zero Page
+
|-
</td><td>DEC $zz
+
| Absolute || DEC $aaaa || $ce || 3 || 7
</td><td>$c6
+
|-
</td><td>2
+
| Absolute, X || DEC $aaaa,X || $de || 3 || 7
</td><td>6
+
|}
  
</td></tr>
 
<tr>
 
<td>Zero Page, X
 
</td><td>DEC $zz,X
 
</td><td>$d6
 
</td><td>2
 
</td><td>6
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>DEC $aaaa
 
</td><td>$ce
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
 
</td><td>DEC $aaaa,X
 
</td><td>$de
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== DEX - Decrement X ==
 
== DEX - Decrement X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
  
<tr style="background: #efefef">
+
Decrement the X register by 1.
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
  
</td><td><b>D</b>
+
{|
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
| N || Negative Flag || Set if bit 7 of the X register is set
</td><td><b>C</b>
+
|-
</td></tr>
+
| V || Overflow Flag || N/A
<tr>
+
|-
<td>?
+
| T || T Flag || 0
</td><td>
+
|-
</td><td>0
+
| D || Decimal Flag || N/A
</td><td>
+
|-
</td><td>
+
| I || Interrupt Disable || N/A
</td><td>?
+
|-
</td><td>
+
| Z || Zero Flag || Set if the X register is zero
 +
|-
 +
| C || Carry Flag || N/A
 +
|-
 +
|}
  
</td></tr></table>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
  
<tr style="background: #efefef">
+
{| class="addressing"
<td><b>Addressing Mode</b>
+
|-
</td><td><b>Syntax</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>Opcode</b>
+
|-
</td><td><b>Bytes</b>
+
| Implied || DEX || $ca || 1 || 2
</td><td><b>Cycles</b>
+
|}
</td></tr>
+
<tr>
+
<td>Implied
+
  
</td><td>DEX
 
</td><td>$ca
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== DEY - Decrement Y ==
 
== DEY - Decrement Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
  
<tr style="background: #efefef">
+
Decrement the Y register by 1.
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
  
</td><td><b>D</b>
+
{|
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
| N || Negative Flag || Set if bit 7 of the Y register is set
</td><td><b>C</b>
+
|-
</td></tr>
+
| V || Overflow Flag || N/A
<tr>
+
|-
<td>?
+
| T || T Flag || 0
</td><td>
+
|-
</td><td>0
+
| D || Decimal Flag || N/A
</td><td>
+
|-
</td><td>
+
| I || Interrupt Disable || N/A
</td><td>?
+
|-
</td><td>
+
| Z || Zero Flag || Set if the Y register is zero
 +
|-
 +
| C || Carry Flag || N/A
 +
|-
 +
|}
  
</td></tr></table>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
  
<tr style="background: #efefef">
+
{| class="addressing"
<td><b>Addressing Mode</b>
+
|-
</td><td><b>Syntax</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>Opcode</b>
+
|-
</td><td><b>Bytes</b>
+
| Implied || DEY || $88 || 1 || 2
</td><td><b>Cycles</b>
+
|}
</td></tr>
+
<tr>
+
<td>Implied
+
  
</td><td>DEY
 
</td><td>$88
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== EOR - Exclusive OR Accumulator with Memory ==
 
== EOR - Exclusive OR Accumulator with Memory ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
 +
<p>Logically [[XOR]] the value referenced by the operand to the accumulator.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Immediate || EOR #$ii || $49 || 2 || 2
 +
|-
 +
| Zero Page || EOR $zz || $45 || 2 || 4
 +
|-
 +
| Zero Page, X || EOR $zz,X || $55 || 2 || 4
 +
|-
 +
| Absolute || EOR $aaaa || $4d || 3 || 5
 +
|-
 +
| Absolute, X || EOR $aaaa,X || $5d || 3 || 5
 +
|-
 +
| Absolute, Y || EOR $aaaa,Y || $59 || 3 || 5
 +
|-
 +
| Indirect || EOR ($zzzz) || $52 || 3 || 7
 +
|-
 +
| Indexed Indirect || EOR ($zz,X) || $41 || 2 || 7
 +
|-
 +
| Indirect, Index || EOR ($zz),Y || $51 || 2 || 7
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>?
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>
 
 
</td></tr></table>
 
<p>Logically <a href="/index.php/XOR" title="XOR">XOR</a> the value referenced by the operand to the accumulator.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
</td><td>EOR #$ii
 
</td><td>$49
 
</td><td>2
 
</td><td>2
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>EOR $zz
 
</td><td>$45
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
 
<tr>
 
<td>Zero Page, X
 
</td><td>EOR $zz,X
 
</td><td>$55
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>EOR $aaaa
 
</td><td>$4d
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>EOR $aaaa,X
 
 
</td><td>$5d
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, Y
 
</td><td>EOR $aaaa,Y
 
</td><td>$59
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Indirect
 
</td><td>EOR ($zz)
 
</td><td>$52
 
</td><td>3
 
</td><td>7
 
 
</td></tr>
 
<tr>
 
<td>Indexed Indirect
 
</td><td>EOR ($zz,X)
 
</td><td>$41
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indirect, Index
 
</td><td>EOR ($zz),Y
 
</td><td>$51
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== INC - Increment ==
 
== INC - Increment ==
 +
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
 +
<p>Increments the value of the location specified by the operand by one.  The Carry flag is not used, nor is it modified.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Accumulator || INC A || $1a || 1 || 2
 +
|-
 +
| Zero Page || INC $zz || $e6 || 2 || 6
 +
|-
 +
| Zero Page, X || INC $zz,X || $f6 || 2 || 6
 +
|-
 +
| Absolute || INC $aaaa || $ee || 3 || 7
 +
|-
 +
| Absolute, X || INC $aaaa,X || $fe || 3 || 7
 +
|}
  
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
 
</td></tr>
 
<tr>
 
<td>?
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>
 
</td></tr></table>
 
<p>Increments the value of the location specified by the operand by one.  The Carry flag is not used, nor is it modified.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Accumulator
 
</td><td>INC A
 
</td><td>$1a
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
<tr>
 
 
<td>Zero Page
 
</td><td>INC $zz
 
</td><td>$e6
 
</td><td>2
 
</td><td>6
 
</td></tr>
 
<tr>
 
<td>Zero Page, X
 
</td><td>INC $zz,X
 
</td><td>$f6
 
</td><td>2
 
</td><td>6
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>INC $aaaa
 
</td><td>$ee
 
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>INC $aaaa,X
 
</td><td>$fe
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== INX - Increment X ==
 
== INX - Increment X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
 +
<p>Increments the value in the X register by one.  The Carry flag is not used, nor is it modified.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || INX || $e8 || 1 || 2
 +
|}
  
<tr style="background: #efefef">
 
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>?
 
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>
 
</td></tr></table>
 
<p>Increments the value in the X register by one.  The Carry flag is not used, nor is it modified.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>INX
 
</td><td>$e8
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== INY - Increment Y ==
 
== INY - Increment Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| ? || || 0 || || || ? || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
<p>Increments the value in the Y register by one.  The Carry flag is not used, nor is it modified.</p>
</td><td><b>I</b>
+
{| class="addressing"
</td><td><b>Z</b>
+
|-
</td><td><b>C</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td></tr>
+
|-
 
+
| Implied || INY || $c8 || 1 || 2
<tr>
+
|}
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Increments the value in the Y register by one.  The Carry flag is not used, nor is it modified.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
  
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>INY
 
</td><td>$c8
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== JMP - Jump ==
 
== JMP - Jump ==
 +
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
 +
<p>Transfers control(sets the program counter) to the effective address calculated from the operand.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Absolute || JMP $aaaa || $4c || 3 || 4
 +
|-
 +
| Indirect || JMP ($zzzz) || $6c || 3 || 7
 +
|-
 +
| Indexed Indirect || JMP ($zzzz,X) || $7c || 3 || 7
 +
|}
  
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<p>Transfers control(sets the program counter) to the effective address calculated from the operand.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>JMP $aaaa
 
</td><td>$4c
 
</td><td>3
 
</td><td>4
 
</td></tr>
 
<tr>
 
 
<td>Indirect
 
</td><td>JMP ($aaaa)
 
</td><td>$6c
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indexed Indirect
 
</td><td>JMP ($aaaa,X)
 
</td><td>$7c
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== JSR - Jump to Subroutine ==
 
== JSR - Jump to Subroutine ==
 +
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
  
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
Push the current program counter value (minus 1) onto the stack and set it to the address specified in the second operand.
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
  
<tr style="background: #efefef">
+
{| class="addressing"
<td><b>Addressing Mode</b>
+
|-
</td><td><b>Syntax</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Absolute || JSR $aaaa || $20 || 3 || 7
 +
|}
  
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>JSR $aaaa
 
</td><td>$20
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== LDA - Load Accumulator ==
 
== LDA - Load Accumulator ==
 +
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
 +
<p>Loads the accumulator with the value at the effective address.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Immediate || LDA #$ii || $a9 || 2 || 2
 +
|-
 +
| Zero Page || LDA $zz || $a5 || 2 || 4
 +
|-
 +
| Zero Page, X || LDA $zz,X || $b5 || 2 || 4
 +
|-
 +
| Absolute || LDA $aaaa || $ad || 3 || 5
 +
|-
 +
| Absolute, X || LDA $aaaa,X || $bd || 3 || 5
 +
|-
 +
| Absolute, Y || LDA $aaaa,Y || $b9 || 3 || 5
 +
|-
 +
| Indirect || LDA ($zzzz) || $b2 || 3 || 7
 +
|-
 +
| Indexed Indirect || LDA ($zz,X) || $a1 || 2 || 7
 +
|-
 +
| Indirect, Index || LDA ($zz),Y || $b1 || 2 || 7
 +
|}
  
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
 
</td></tr>
 
<tr>
 
<td>?
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>
 
</td></tr></table>
 
<p>Loads the accumulator with the value at the effective address.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
</td><td>LDA #$ii
 
</td><td>$a9
 
</td><td>2
 
</td><td>2
 
</td></tr>
 
<tr>
 
 
<td>Zero Page
 
</td><td>LDA $zz
 
</td><td>$a5
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Zero Page, X
 
</td><td>LDA $zz,X
 
</td><td>$b5
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>LDA $aaaa
 
</td><td>$ad
 
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>LDA $aaaa,X
 
</td><td>$bd
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, Y
 
</td><td>LDA $aaaa,Y
 
</td><td>$b9
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
 
<tr>
 
<td>Indirect
 
</td><td>LDA ($zz)
 
</td><td>$b2
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indexed Indirect
 
</td><td>LDA ($zz,X)
 
</td><td>$a1
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indirect, Index
 
</td><td>LDA ($zz),Y
 
 
</td><td>$b1
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== LDX - Load X ==
 
== LDX - Load X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| ? || || 0 || || || ? || 
</td><td><b>T</b>
+
|}
 
+
<p>Loads the X register with the value at the effective address.</p>
</td><td><b>D</b>
+
{| class="addressing"
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Immediate || LDX #$ii || $a2 || 2 || 2
<tr>
+
|-
<td>?
+
| Zero Page || LDX $zz || $a6 || 2 || 4
</td><td>
+
|-
</td><td>0
+
| Zero Page, Y || LDX $zz,Y || $b6 || 2 || 4
</td><td>
+
|-
</td><td>
+
| Absolute || LDX $aaaa || $ae || 3 || 5
</td><td>?
+
|-
</td><td>
+
| Absolute, Y || LDX $aaaa,Y || $be || 3 || 5
 
+
|}
</td></tr></table>
+
<p>Loads the X register with the value at the effective address.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
 
+
<tr>
+
<td>Immediate
+
</td><td>LDX #$ii
+
</td><td>$a2
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>LDX $zz
+
</td><td>$a6
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, Y
+
</td><td>LDX $zz,Y
+
 
+
</td><td>$b6
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>LDX $aaaa
+
</td><td>$ae
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>LDX $aaaa,Y
+
</td><td>$be
+
</td><td>3
+
</td><td>5
+
  
</td></tr>
 
</table>
 
 
== LDY - Load Y ==
 
== LDY - Load Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
 +
<p>Loads the Y register with the value at the effective address.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Immediate || LDY #$ii || $a0 || 2 || 2
 +
|-
 +
| Zero Page || LDY $zz || $a4 || 2 || 4
 +
|-
 +
| Zero Page, X || LDY $zz,X || $b4 || 2 || 4
 +
|-
 +
| Absolute || LDY $aaaa || $ac || 3 || 5
 +
|-
 +
| Absolute, X || LDY $aaaa,X || $bc || 3 || 5
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>?
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>
 
</td></tr></table>
 
<p>Loads the Y register with the value at the effective address.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
</td><td>LDY #$ii
 
</td><td>$a0
 
 
</td><td>2
 
</td><td>2
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>LDY $zz
 
</td><td>$a4
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Zero Page, X
 
</td><td>LDY $zz,X
 
</td><td>$b4
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
 
<tr>
 
<td>Absolute
 
</td><td>LDY $aaaa
 
</td><td>$ac
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>LDY $aaaa,X
 
</td><td>$bc
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
</table>
 
 
== LSR - Logical Shift Right ==
 
== LSR - Logical Shift Right ==
 +
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 0
 +
|}
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Accumulator || LSR A || $4a || 1 || 2
 +
|-
 +
| Zero Page || LSR $zz || $46 || 2 || 6
 +
|-
 +
| Zero Page, X || LSR $zz,X || $56 || 2 || 6
 +
|-
 +
| Absolute || LSR $aaaa || $4e || 3 || 7
 +
|-
 +
| Absolute, X || LSR $aaaa,X || $5e || 3 || 7
 +
|}
  
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
 
</td></tr>
 
<tr>
 
<td>?
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>0
 
</td></tr></table>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Accumulator
 
</td><td>LSR A
 
</td><td>$4a
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>LSR $zz
 
 
</td><td>$46
 
</td><td>2
 
</td><td>6
 
</td></tr>
 
<tr>
 
<td>Zero Page, X
 
</td><td>LSR $zz,X
 
</td><td>$56
 
</td><td>2
 
</td><td>6
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>LSR $aaaa
 
</td><td>$4e
 
</td><td>3
 
</td><td>7
 
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>LSR $aaaa,X
 
</td><td>$5e
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== NOP - No Operation ==
 
== NOP - No Operation ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || NOP || $ea || 1 || 2
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
 
</td><td>
 
</td><td>
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>NOP
 
</td><td>$ea
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== ORA - OR Accumulator with Memory ==
 
== ORA - OR Accumulator with Memory ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
 
+
| ? || || 0 || || || ? || 
</td><td><b>V</b>
+
|}
</td><td><b>T</b>
+
<p>Logically [[OR]] the value referenced by the operand with the accumulator, storing the result in the accumulator.</p>
</td><td><b>D</b>
+
{| class="addressing"
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Immediate || ORA #$ii || $09 || 2 || 2
<tr>
+
|-
<td>?
+
| Zero Page || ORA $zz || $05 || 2 || 4
</td><td>
+
|-
</td><td>0
+
| Zero Page, X || ORA $zz,X || $15 || 2 || 4
 
+
|-
</td><td>
+
| Absolute || ORA $aaaa || $0d || 3 || 5
</td><td>
+
|-
</td><td>?
+
| Absolute, X || ORA $aaaa,X || $1d || 3 || 5
</td><td>
+
|-
</td></tr></table>
+
| Absolute, Y || ORA $aaaa,Y || $19 || 3 || 5
<p>Logically <a href="/index.php?title=OR&amp;action=edit" class="new" title="OR">OR</a> the value referenced by the operand with the accumulator, storing the result in the accumulator.
+
|-
</p>
+
| Indirect || ORA ($zzzz) || $12 || 3 || 7
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 
+
| Indexed Indirect || ORA ($zz,X) || $01 || 2 || 7
<tr style="background: #efefef">
+
|-
<td><b>Addressing Mode</b>
+
| Indirect, Index || ORA ($zz),Y || $11 || 2 || 7
</td><td><b>Syntax</b>
+
|}
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>ORA #$ii
+
</td><td>$09
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>ORA $zz
+
 
+
</td><td>$05
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>ORA $zz,X
+
</td><td>$15
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>ORA $aaaa
+
</td><td>$0d
+
</td><td>3
+
</td><td>5
+
 
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>ORA $aaaa,X
+
</td><td>$1d
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>ORA $aaaa,Y
+
</td><td>$19
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Indirect
+
 
+
</td><td>ORA ($zz)
+
</td><td>$12
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
</td><td>ORA ($zz,X)
+
</td><td>$01
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indirect, Index
+
</td><td>ORA ($zz),Y
+
</td><td>$11
+
</td><td>2
+
  
</td><td>7
 
</td></tr>
 
</table>
 
 
== PHA - Push A ==
 
== PHA - Push A ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
 +
<p>Pushes the accumulator to the stack.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || PHA || $48 || 1 || 3
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<p>Pushes the accumulator to the stack.
 
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
 
</td><td>PHA
 
</td><td>$48
 
</td><td>1
 
</td><td>3
 
</td></tr>
 
</table>
 
 
== PHP - Push P ==
 
== PHP - Push P ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
 
+
<p>Pushes the status flags(1 byte) to the stack.</p>
</td><td><b>D</b>
+
{| class="addressing"
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Implied || PHP || $08 || 1 || 3
<tr>
+
|}
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
 
+
</td></tr></table>
+
<p>Pushes the status flags(1 byte) to the stack.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
  
<tr>
 
<td>Implied
 
</td><td>PHP
 
</td><td>$08
 
</td><td>1
 
</td><td>3
 
</td></tr>
 
</table>
 
 
== PHX - Push X ==
 
== PHX - Push X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
 +
<p>Pushes the X register to the stack.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || PHX || $da || 1 || 3
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<p>Pushes the X register to the stack.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>PHX
 
</td><td>$da
 
</td><td>1
 
</td><td>3
 
</td></tr>
 
</table>
 
 
== PHY - Push Y ==
 
== PHY - Push Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
 
+
| || || 0 || || || || 
</td><td><b>V</b>
+
|}
</td><td><b>T</b>
+
<p>Pushes the Y register to the stack.</p>
</td><td><b>D</b>
+
{| class="addressing"
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Implied || PHY || $5a || 1 || 3
<tr>
+
|}
<td>
+
</td><td>
+
</td><td>0
+
 
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Pushes the Y register to the stack.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
  
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>PHY
 
</td><td>$5a
 
</td><td>1
 
</td><td>3
 
</td></tr>
 
</table>
 
 
== PLA - Pull A ==
 
== PLA - Pull A ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
 +
<p>Pulls a value off the stack, and stores the value in the accumulator.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || PLA || $68 || 1 || 4
 +
|}
  
<tr style="background: #efefef">
 
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>?
 
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>
 
</td></tr></table>
 
<p>Pulls a value off the stack, and stores the value in the accumulator.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>PLA
 
</td><td>$68
 
</td><td>1
 
</td><td>4
 
</td></tr>
 
</table>
 
 
== PLP - Pull P ==
 
== PLP - Pull P ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || ? || ? || ? || ? || ? || ?
 +
|}
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || PLP || $28 || 1 || 4
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
 
<tr>
 
<td>?
 
</td><td>?
 
</td><td>?
 
</td><td>?
 
</td><td>?
 
</td><td>?
 
</td><td>?
 
</td></tr></table>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>PLP
 
</td><td>$28
 
</td><td>1
 
</td><td>4
 
</td></tr>
 
</table>
 
<p><br />
 
</p>
 
 
== PLX - Pull X ==
 
== PLX - Pull X ==
 
+
{|
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|-
 
+
! N !! V !! T !! D !! I !! Z !! C
<tr style="background: #efefef">
+
|-
<td><b>N</b>
+
| ? || || 0 || || || ? || 
</td><td><b>V</b>
+
|}
</td><td><b>T</b>
+
<p>Pulls a value off the stack, and stores the value in the X register.</p>
</td><td><b>D</b>
+
{| class="addressing"
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
 
+
| Implied || PLX || $fa || 1 || 4
</td></tr>
+
|}
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Pulls a value off the stack, and stores the value in the X register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>PLX
+
</td><td>$fa
+
</td><td>1
+
</td><td>4
+
</td></tr>
+
</table>
+
  
 
== PLY - Pull Y ==
 
== PLY - Pull Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || 
 +
|}
 +
<p>Pulls a value off the stack, and stores the value in Y register.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || PLY || $7a || 1 || 4
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>?
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>
 
</td></tr></table>
 
<p>Pulls a value off the stack, and stores the value in Y register.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>PLY
 
</td><td>$7a
 
</td><td>1
 
</td><td>4
 
 
</td></tr>
 
</table>
 
 
== RMBn - Reset Memory Bit n ==
 
== RMBn - Reset Memory Bit n ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
<p>Reads the zero-page address specified by the operand, resets(clears) the bit "n", and then writes it back to the aforementioned address.</p>
</td><td><b>I</b>
+
{| class="addressing"
 
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Zero Page || RMB0 $zz || $07 || 2 || 7
<tr>
+
|-
<td>
+
| Zero Page || RMB1 $zz || $17 || 2 || 7
</td><td>
+
|-
</td><td>0
+
| Zero Page || RMB2 $zz || $27 || 2 || 7
</td><td>
+
|-
</td><td>
+
| Zero Page || RMB3 $zz || $37 || 2 || 7
</td><td>
+
|-
</td><td>
+
| Zero Page || RMB4 $zz || $47 || 2 || 7
</td></tr></table>
+
|-
<p>Reads the zero-page address specified by the operand, resets(clears) the bit "n", and then writes it back to the aforementioned address.
+
| Zero Page || RMB5 $zz || $57 || 2 || 7
</p>
+
|-
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
| Zero Page || RMB6 $zz || $67 || 2 || 7
 
+
|-
<tr style="background: #efefef">
+
| Zero Page || RMB7 $zz || $77 || 2 || 7
<td><b>Addressing Mode</b>
+
|}
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB0 $zz
+
</td><td>$07
+
 
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB1 $zz
+
</td><td>$17
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB2 $zz
+
</td><td>$27
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
 
+
<tr>
+
<td>Zero Page
+
</td><td>RMB3 $zz
+
</td><td>$37
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB4 $zz
+
</td><td>$47
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB5 $zz
+
 
+
</td><td>$57
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB6 $zz
+
</td><td>$67
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB7 $zz
+
</td><td>$77
+
</td><td>2
+
</td><td>7
+
  
</td></tr>
 
</table>
 
 
== ROL - Rotate Left ==
 
== ROL - Rotate Left ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || || 0 || || || ? || ?
 +
|}
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Accumulator || ROL A || $2a || 1 || 2
 +
|-
 +
| Zero Page || ROL $zz || $26 || 2 || 6
 +
|-
 +
| Zero Page, X || ROL $zz,X || $36 || 2 || 6
 +
|-
 +
| Absolute || ROL $aaaa || $2e || 3 || 7
 +
|-
 +
| Absolute, X || ROL $aaaa,X || $3e || 3 || 7
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>?
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>?
 
</td></tr></table>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Accumulator
 
</td><td>ROL A
 
</td><td>$2a
 
</td><td>1
 
</td><td>2
 
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>ROL $zz
 
</td><td>$26
 
</td><td>2
 
</td><td>6
 
</td></tr>
 
<tr>
 
<td>Zero Page, X
 
</td><td>ROL $zz,X
 
</td><td>$36
 
</td><td>2
 
</td><td>6
 
</td></tr>
 
<tr>
 
<td>Absolute
 
 
</td><td>ROL $aaaa
 
</td><td>$2e
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>ROL $aaaa,X
 
</td><td>$3e
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== ROR - Rotate Right ==
 
== ROR - Rotate Right ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| ? || || 0 || || || ? || ?
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
{| class="addressing"
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Accumulator || ROR A || $6a || 1 || 2
 
+
|-
<tr>
+
| Zero Page || ROR $zz || $66 || 2 || 6
<td>?
+
|-
</td><td>
+
| Zero Page, X || ROR $zz,X || $76 || 2 || 6
</td><td>0
+
|-
</td><td>
+
| Absolute || ROR $aaaa || $6e || 3 || 7
</td><td>
+
|-
</td><td>?
+
| Absolute, X || ROR $aaaa,X || $7e || 3 || 7
</td><td>?
+
|}
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Accumulator
+
</td><td>ROR A
+
</td><td>$6a
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>ROR $zz
+
</td><td>$66
+
</td><td>2
+
 
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>ROR $zz,X
+
</td><td>$76
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>ROR $aaaa
+
</td><td>$6e
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
  
<td>Absolute, X
 
</td><td>ROR $aaaa,X
 
</td><td>$7e
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== RTI - Return from Interrupt ==
 
== RTI - Return from Interrupt ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || ? || ? || ? || ? || ? || ?
 +
|}
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || RTI || $40 || 1 || 7
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>?
 
</td><td>?
 
</td><td>?
 
</td><td>?
 
</td><td>?
 
 
</td><td>?
 
</td><td>?
 
</td></tr></table>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
 
<tr>
 
<td>Implied
 
</td><td>RTI
 
</td><td>$40
 
</td><td>1
 
</td><td>7
 
</td></tr>
 
</table>
 
<p><br />
 
</p>
 
 
== RTS - Return from Subroutine ==
 
== RTS - Return from Subroutine ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || RTS || $60 || 1 || 7
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
 
</td><td>
 
</td><td>
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>RTS
 
</td><td>$60
 
</td><td>1
 
</td><td>7
 
</td></tr>
 
</table>
 
<p><br />
 
</p>
 
 
== SAX - Swap A and X ==
 
== SAX - Swap A and X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
 +
<p>Swaps the values in the accumulator and X register.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || SAX || $22 || 1 || 3
 +
|}
  
<tr style="background: #efefef">
 
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>
 
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<p>Swaps the values in the accumulator and X register.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>SAX
 
</td><td>$22
 
</td><td>1
 
</td><td>3
 
</td></tr>
 
</table>
 
 
== SAY - Swap A and Y ==
 
== SAY - Swap A and Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
<p>Swap the values in the accumulator and Y register.</p>
</td><td><b>I</b>
+
{| class="addressing"
</td><td><b>Z</b>
+
|-
</td><td><b>C</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td></tr>
+
|-
 
+
| Implied || SAY || $42 || 1 || 3
<tr>
+
|}
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Swap the values in the accumulator and Y register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
  
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>SAY
 
</td><td>$42
 
</td><td>1
 
</td><td>3
 
</td></tr>
 
</table>
 
 
== SBC - Subtract with Borrow ==
 
== SBC - Subtract with Borrow ==
 +
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| ? || ? || 0 || || || ? || ?
 +
|}
 +
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).</p>
 +
<p>The overflow flag is not affected by this instruction if in Decimal mode.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Immediate || SBC #$ii || $e9 || 2 || 2
 +
|-
 +
| Zero Page || SBC $zz || $e5 || 2 || 4
 +
|-
 +
| Zero Page, X || SBC $zz,X || $f5 || 2 || 4
 +
|-
 +
| Absolute || SBC $aaaa || $ed || 3 || 5
 +
|-
 +
| Absolute, X || SBC $aaaa,X || $fd || 3 || 5
 +
|-
 +
| Absolute, Y || SBC $aaaa,Y || $f9 || 3 || 5
 +
|-
 +
| Indirect || SBC ($zzzz) || $f2 || 3 || 7
 +
|-
 +
| Indexed Indirect || SBC ($zz,X) || $e1 || 2 || 7
 +
|-
 +
| Indirect, Index || SBC ($zz),Y || $f1 || 2 || 7
 +
|}
  
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
 
</td></tr>
 
<tr>
 
<td>?
 
</td><td>?
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>?
 
</td><td>?
 
</td></tr></table>
 
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).
 
</p><p>The overflow flag is not affected by this instruction if in Decimal mode.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
</td><td>SBC #$ii
 
</td><td>$e9
 
</td><td>2
 
</td><td>2
 
</td></tr>
 
<tr>
 
 
<td>Zero Page
 
</td><td>SBC $zz
 
</td><td>$e5
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Zero Page, X
 
</td><td>SBC $zz,X
 
</td><td>$f5
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>SBC $aaaa
 
</td><td>$ed
 
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, X
 
</td><td>SBC $aaaa,X
 
</td><td>$fd
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
<tr>
 
<td>Absolute, Y
 
</td><td>SBC $aaaa,Y
 
</td><td>$f9
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
 
<tr>
 
<td>Indirect
 
</td><td>SBC ($zz)
 
</td><td>$f2
 
</td><td>3
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indexed Indirect
 
</td><td>SBC ($zz,X)
 
</td><td>$e1
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indirect, Index
 
</td><td>SBC ($zz),Y
 
 
</td><td>$f1
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== SEC - Set Carry Flag ==
 
== SEC - Set Carry Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 1
</td><td><b>T</b>
+
|}
 
+
<p>Sets the carry flag.</p>
</td><td><b>D</b>
+
{| class="addressing"
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Implied || SEC || $38 || 1 || 2
<tr>
+
|}
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>1
+
 
+
</td></tr></table>
+
<p>Sets the carry flag.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
  
<tr>
 
<td>Implied
 
</td><td>SEC
 
</td><td>$38
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== SED - Set Decimal Flag ==
 
== SED - Set Decimal Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || 1 || || || 
 +
|}
 +
<p>Sets the decimal flag, enabling [[Decimal Mode | decimal mode]].</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Implied || SED || $f8 || 1 || 2
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
</td><td>1
 
</td><td>
 
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<p>Sets the decimal flag, enabling <a href="/index.php?title=decimal_mode&amp;action=edit" class="new" title="decimal_mode">decimal mode</a>.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>SED
 
</td><td>$f8
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== SEI - Set Interrupt Flag ==
 
== SEI - Set Interrupt Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
 
+
|-
<td><b>N</b>
+
| || || 0 || || 1 || || 
</td><td><b>V</b>
+
|}
</td><td><b>T</b>
+
<p>Sets the interrupt flag, preventing IRQs from being processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).</p>
</td><td><b>D</b>
+
{| class="addressing"
</td><td><b>I</b>
+
|-
</td><td><b>Z</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td><td><b>C</b>
+
|-
</td></tr>
+
| Implied || SEI || $78 || 1 || 2
<tr>
+
|}
<td>
+
 
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>1
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Sets the interrupt flag, preventing IRQs from being processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
  
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Implied
 
</td><td>SEI
 
</td><td>$78
 
</td><td>1
 
</td><td>2
 
</td></tr>
 
</table>
 
 
== SET - Set T Flag ==
 
== SET - Set T Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 1 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
<p>Sets the T flag, which changes the behavior of the next instruction if the next instruction is ADC, AND, EOR, ORA, or SBC, in which case the operation is performed on the zero-page address specified by the X register, instead of the accumulator.</p>
</td><td><b>I</b>
+
<p>Note that interrupt processing preserves the T-flag, and clears the T-flag in the interrupt handler, so a programmer needn't worry about an interrupt
</td><td><b>Z</b>
+
occuring between SET and the next instruction.</p>
</td><td><b>C</b>
+
{| class="addressing"
</td></tr>
+
|-
 
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
<tr>
+
|-
<td>
+
| Implied || SET || $f4 || 1 || 2
</td><td>
+
|}
</td><td>1
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Sets the T flag, which changes the behavior of the next instruction if the next instruction is ADC, AND, EOR, ORA, or SBC, in which case the operation is performed on the zero-page address specified by the X register, instead of the accumulator.
+
</p><p>Note that interrupt processing preserves the T-flag, and clears the T-flag in the interrupt handler, so a programmer needn't worry about an interrupt
+
occuring between SET and the next instruction.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>SET
+
</td><td>$f4
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
  
 
== SMBn - Set Memory Bit n ==
 
== SMBn - Set Memory Bit n ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
 +
<p>Reads the zero-page address specified by the operand, sets the bit "n", and then writes it back to the aforementioned address.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Zero Page || SMB0 $zz || $87 || 2 || 7
 +
|-
 +
| Zero Page || SMB1 $zz || $97 || 2 || 7
 +
|-
 +
| Zero Page || SMB2 $zz || $a7 || 2 || 7
 +
|-
 +
| Zero Page || SMB3 $zz || $b7 || 2 || 7
 +
|-
 +
| Zero Page || SMB4 $zz || $c7 || 2 || 7
 +
|-
 +
| Zero Page || SMB5 $zz || $d7 || 2 || 7
 +
|-
 +
| Zero Page || SMB6 $zz || $e7 || 2 || 7
 +
|-
 +
| Zero Page || SMB7 $zz || $f7 || 2 || 7
 +
|}
  
<tr style="background: #efefef">
+
== ST0 - Store [[HuC6270 | (HuC6270) VDC]] No. 0 ==
<td><b>N</b>
+
{|
</td><td><b>V</b>
+
|-
</td><td><b>T</b>
+
! N !! V !! T !! D !! I !! Z !! C
</td><td><b>D</b>
+
|-
</td><td><b>I</b>
+
| || || 0 || || || || 
</td><td><b>Z</b>
+
|}
 +
<p>Writes the immediate value to the physical address $1FE000, the [[HuC6270 | (HuC6270) VDC]]'s address register.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Immediate || ST0 #$ii || $03 || 2 || 5
 +
|}
  
</td><td><b>C</b>
+
== ST1 - Store [[HuC6270 | (HuC6270) VDC]] No. 1 ==
</td></tr>
+
{|
<tr>
+
|-
<td>
+
! N !! V !! T !! D !! I !! Z !! C
</td><td>
+
|-
</td><td>0
+
| || || 0 || || || || 
</td><td>
+
|}
</td><td>
+
<p>Writes the immediate value to the physical address $1FE002, the [[HuC6270 | (HuC6270) VDC]]'s lower data register.</p>
</td><td>
+
{| class="addressing"
</td><td>
+
|-
</td></tr></table>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
<p>Reads the zero-page address specified by the operand, sets the bit "n", and then writes it back to the aforementioned address.
+
|-
</p>
+
| Immediate || ST1 #$ii || $13 || 2 || 5
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
|}
  
<tr style="background: #efefef">
+
== ST2 - Store [[HuC6270 | (HuC6270) VDC]] No. 2 ==
 +
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
 +
<p>Writes the immediate value to the physical address $1FE003, the [[HuC6270 | (HuC6270) VDC]]'s upper data register.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Immediate || ST2 #$ii || $23 || 2 || 5
 +
|}
  
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>SMB0 $zz
 
</td><td>$87
 
</td><td>2
 
</td><td>7
 
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>SMB1 $zz
 
</td><td>$97
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>SMB2 $zz
 
</td><td>$a7
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
 
</td><td>SMB3 $zz
 
</td><td>$b7
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>SMB4 $zz
 
</td><td>$c7
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>SMB5 $zz
 
</td><td>$d7
 
</td><td>2
 
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>SMB6 $zz
 
</td><td>$e7
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>SMB7 $zz
 
</td><td>$f7
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
 
</table>
 
== ST0 - Store <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> No. 0 ==
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>
 
</td><td>
 
 
</td></tr></table>
 
<p>Writes the immediate value to the physical address $1FE000, the <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a>'s address register.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
</td><td>ST0 #$ii
 
</td><td>$03
 
</td><td>2
 
</td><td>5
 
</td></tr>
 
</table>
 
== ST1 - Store <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> No. 1 ==
 
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<p>Writes the immediate value to the physical address $1FE002, the <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a>'s lower data register.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
</td><td>ST1 #$ii
 
</td><td>$13
 
</td><td>2
 
 
</td><td>5
 
</td></tr>
 
</table>
 
== ST2 - Store <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> No. 2 ==
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<p>Writes the immediate value to the physical address $1FE003, the <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a>'s upper data register.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
</td><td><b>Opcode</b>
 
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Immediate
 
</td><td>ST2 #$ii
 
</td><td>$23
 
</td><td>2
 
</td><td>5
 
</td></tr>
 
</table>
 
 
== STA - Store Accumulator ==
 
== STA - Store Accumulator ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 
+
|-
<tr style="background: #efefef">
+
! N !! V !! T !! D !! I !! Z !! C
<td><b>N</b>
+
|-
</td><td><b>V</b>
+
| || || 0 || || || || 
</td><td><b>T</b>
+
|}
</td><td><b>D</b>
+
<p>Stores the value in the accumulator to the effective address specified by the operand.</p>
</td><td><b>I</b>
+
{| class="addressing"
</td><td><b>Z</b>
+
|-
</td><td><b>C</b>
+
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
</td></tr>
+
|-
 
+
| Zero Page || STA $zz || $85 || 2 || 4
<tr>
+
|-
<td>
+
| Zero Page, X || STA $zz,X || $95 || 2 || 4
</td><td>
+
|-
</td><td>0
+
| Absolute || STA $aaaa || $8d || 3 || 5
</td><td>
+
|-
</td><td>
+
| Absolute, X || STA $aaaa,X || $9d || 3 || 5
</td><td>
+
|-
</td><td>
+
| Absolute, Y || STA $aaaa,Y || $99 || 3 || 5
</td></tr></table>
+
|-
<p>Stores the value in the accumulator to the effective address specified by the operand.
+
| Indirect || STA ($zzzz) || $92 || 3 || 7
</p>
+
|-
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
| Indexed Indirect || STA ($zz,X) || $81 || 2 || 7
 
+
|-
<tr style="background: #efefef">
+
| Indirect, Index || STA ($zz),Y || $91 || 2 || 7
<td><b>Addressing Mode</b>
+
|}
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>STA $zz
+
</td><td>$85
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>STA $zz,X
+
 
+
</td><td>$95
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>STA $aaaa
+
</td><td>$8d
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>STA $aaaa,X
+
</td><td>$9d
+
</td><td>3
+
</td><td>5
+
 
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>STA $aaaa,Y
+
</td><td>$99
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Indirect
+
</td><td>STA ($zz)
+
</td><td>$92
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
  
</td><td>STA ($zz,X)
 
</td><td>$81
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
<tr>
 
<td>Indirect, Index
 
</td><td>STA ($zz),Y
 
</td><td>$91
 
</td><td>2
 
</td><td>7
 
</td></tr>
 
</table>
 
 
== STX - Store X ==
 
== STX - Store X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-
 +
! N !! V !! T !! D !! I !! Z !! C
 +
|-
 +
| || || 0 || || || || 
 +
|}
 +
<p>Stores the value in the X register to the effective address specified by the operand.</p>
 +
{| class="addressing"
 +
|-
 +
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 +
|-
 +
| Zero Page || STX $zz || $86 || 2 || 4
 +
|-
 +
| Zero Page, Y || STX $zz,Y || $96 || 2 || 4
 +
|-
 +
| Absolute || STX $aaaa || $8e || 3 || 5
 +
|}
  
<tr style="background: #efefef">
 
<td><b>N</b>
 
</td><td><b>V</b>
 
</td><td><b>T</b>
 
</td><td><b>D</b>
 
</td><td><b>I</b>
 
</td><td><b>Z</b>
 
</td><td><b>C</b>
 
</td></tr>
 
 
<tr>
 
<td>
 
</td><td>
 
</td><td>0
 
</td><td>
 
</td><td>
 
</td><td>
 
</td><td>
 
</td></tr></table>
 
<p>Stores the value in the X register to the effective address specified by the operand.
 
</p>
 
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
 
 
<tr style="background: #efefef">
 
<td><b>Addressing Mode</b>
 
</td><td><b>Syntax</b>
 
 
</td><td><b>Opcode</b>
 
</td><td><b>Bytes</b>
 
</td><td><b>Cycles</b>
 
</td></tr>
 
<tr>
 
<td>Zero Page
 
</td><td>STX $zz
 
</td><td>$86
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Zero Page, Y
 
</td><td>STX $zz,Y
 
 
</td><td>$96
 
</td><td>2
 
</td><td>4
 
</td></tr>
 
<tr>
 
<td>Absolute
 
</td><td>STX $aaaa
 
</td><td>$8e
 
</td><td>3
 
</td><td>5
 
</td></tr>
 
</table>
 
 
== STY - Store Y ==
 
== STY - Store Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
{|
 +
|-