Difference between revisions of "HuC6280 Instruction Set"

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== ADC - Add with Carry ==
 
== ADC - Add with Carry ==
 
{|
 
{|
Line 4: Line 41:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || ? || 0 || &nbsp; || &nbsp; || ? || ?
+
| ? || ? || 0 || || || ? || ?
 
|}
 
|}
 
<p>Add the value specified by the operand, and 1 if the Carry flag is set, to the value in the accumulator.  If the result is too large to fit in the accumulator, the carry flag will be set, otherwise it will be cleared.</p>
 
<p>Add the value specified by the operand, and 1 if the Carry flag is set, to the value in the accumulator.  If the result is too large to fit in the accumulator, the carry flag will be set, otherwise it will be cleared.</p>
 
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).</p>
 
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).</p>
<p>The overflow flag is not affected by this instruction if in Decimal mode; otherwise, if bit7 of the result&nbsp;!= bit7 of the accumulator before the operation, and bit7 of the accumulator before the operation == bit7 of the value specified by the operand, the overflow flag is set, otherwise it is cleared. In other words, if we were to treat the accumulator and value specified by the operand as [http://en.wikipedia.org/wiki/Two%27s_complement two's complement] numbers, in the range of -128 to 127, the overflow flag will be set if the end result is outside of this range(otherwise it will be cleared).</p>
+
<p>The overflow flag is not affected by this instruction if in Decimal mode; otherwise, if bit 7 of the result != bit  7 of the accumulator before the operation, and bit 7 of the accumulator before the operation == bit 7 of the value specified by the operand, the overflow flag is set, otherwise it is cleared. In other words, if we were to treat the accumulator and value specified by the operand as [http://en.wikipedia.org/wiki/Two%27s_complement two's complement] numbers, in the range of -128 to 127, the overflow flag will be set if the end result is outside of this range(otherwise it will be cleared).</p>
 +
<p>If T=1 (the previous instruction is SET) the zero-page byte specified by the X register is used instead of the A register.</p>
 +
 
 +
<p>Here is a recap of the status register after use :</p>
 
{|
 
{|
 +
|-
 +
| N || Negative Flag || Set if bit 7 is set
 +
|-
 +
| V || Overflow Flag || Set if bit 7 (sign bit for 2's complement number) is incorrect
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if A == 0
 +
|-
 +
| C || Carry Flag || Set if overflow in bit 7 occured
 +
|-
 +
|}
 +
 +
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 25: Line 84:
 
| Absolute, Y || ADC $aaaa,Y || $79 || 3 || 5
 
| Absolute, Y || ADC $aaaa,Y || $79 || 3 || 5
 
|-
 
|-
| Indirect || ADC ($zz) || $72 || 3 || 7
+
| Indirect || ADC ($zzzz) || $72 || 3 || 7
 
|-
 
|-
 
| Indexed Indirect || ADC ($zz,X) || $61 || 2 || 7
 
| Indexed Indirect || ADC ($zz,X) || $61 || 2 || 7
Line 31: Line 90:
 
| Indirect, Index || ADC ($zz),Y || $71 || 2 || 7
 
| Indirect, Index || ADC ($zz),Y || $71 || 2 || 7
 
|}
 
|}
 +
 
== AND - AND Accumulator with Memory ==
 
== AND - AND Accumulator with Memory ==
 
{|
 
{|
Line 36: Line 96:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 +
 +
Performs a bit by bit logical and on the accumulator with the value specified by the operand.
 +
 +
<p>Here is a recap of the processor status flags after use :</p>
 
{|
 
{|
 +
|-
 +
| N || Negative Flag || Set if bit 7 is set
 +
|-
 +
| V || Overflow Flag || N/A
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if A == 0
 +
|-
 +
| C || Carry Flag || N/A
 +
|-
 +
|}
 +
 +
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 54: Line 137:
 
| Absolute, Y || AND $aaaa,Y || $39 || 3 || 5
 
| Absolute, Y || AND $aaaa,Y || $39 || 3 || 5
 
|-
 
|-
| Indirect || AND ($zz) || $32 || 3 || 7
+
| Indirect || AND ($zzzz) || $32 || 3 || 7
 
|-
 
|-
 
| Indexed Indirect || AND ($zz,X) || $21 || 2 || 7
 
| Indexed Indirect || AND ($zz,X) || $21 || 2 || 7
Line 60: Line 143:
 
| Indirect, Index || AND ($zz),Y || $31 || 2 || 7
 
| Indirect, Index || AND ($zz),Y || $31 || 2 || 7
 
|}
 
|}
<p><br /></p>
+
 
 
== ASL - Arithmetic Shift Left ==
 
== ASL - Arithmetic Shift Left ==
 
{|
 
{|
Line 66: Line 149:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || ?
+
| ? || || 0 || || || ? || ?
 
|}
 
|}
<p>Shifts the value at the location specified by the operand left by one bit, shifting in 0 to Bit0, and writes the result back to that location. Bit7 of the value before the shift is copied to the Carry flag.</p>
+
 
 +
<p>Shifts the value at the location specified by the operand left by one bit, shifting in 0 to bit 0, and writes the result back to that location. Bit 7 of the value before the shift is copied to the Carry flag.</p>
 +
 
 
{|
 
{|
 +
|-
 +
| N || Negative Flag || Set if bit 7 of the result is set
 +
|-
 +
| V || Overflow Flag || N/A
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if A == 0
 +
|-
 +
| C || Carry Flag || Set to previous value of bit 7
 +
|-
 +
|}
 +
 +
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 83: Line 187:
 
| Absolute, X || ASL $aaaa,X || $1e || 3 || 7
 
| Absolute, X || ASL $aaaa,X || $1e || 3 || 7
 
|}
 
|}
 +
 
== BBRn - Branch on Bit Reset n ==
 
== BBRn - Branch on Bit Reset n ==
 
{|
 
{|
Line 88: Line 193:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>If Bit 'n' of the value at the effective address specified by the second operand is clear, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If Bit 'n' of the value at the effective address specified by the second operand is clear, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
 
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Zero Page, Relative || BBR0 $zz, $rrrr || $0f || 3 || 6*
+
| Zero Page, Relative || BBR0 $zz, $rr || $0f || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBR1 $zz, $rrrr || $1f || 3 || 6*
+
| Zero Page, Relative || BBR1 $zz, $rr || $1f || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBR2 $zz, $rrrr || $2f || 3 || 6*
+
| Zero Page, Relative || BBR2 $zz, $rr || $2f || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBR3 $zz, $rrrr || $3f || 3 || 6*
+
| Zero Page, Relative || BBR3 $zz, $rr || $3f || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBR4 $zz, $rrrr || $4f || 3 || 6*
+
| Zero Page, Relative || BBR4 $zz, $rr || $4f || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBR5 $zz, $rrrr || $5f || 3 || 6*
+
| Zero Page, Relative || BBR5 $zz, $rr || $5f || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBR6 $zz, $rrrr || $6f || 3 || 6*
+
| Zero Page, Relative || BBR6 $zz, $rr || $6f || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBR7 $zz, $rrrr || $7f || 3 || 6*
+
| Zero Page, Relative || BBR7 $zz, $rr || $7f || 3 || 6*
 
|}
 
|}
 
<pre>* Add 2 extra cycles if branch is taken.</pre>
 
<pre>* Add 2 extra cycles if branch is taken.</pre>
 +
 
== BBSn - Branch on Bit Set n ==
 
== BBSn - Branch on Bit Set n ==
 
{|
 
{|
Line 119: Line 225:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>If Bit 'n' of the value at the effective address specified by the operand is set, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If Bit 'n' of the value at the effective address specified by the operand is set, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
 
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Zero Page, Relative || BBS0 $zz, $rrrr || $8f || 3 || 6*
+
| Zero Page, Relative || BBS0 $zz, $rr || $8f || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBS1 $zz, $rrrr || $9f || 3 || 6*
+
| Zero Page, Relative || BBS1 $zz, $rr || $9f || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBS2 $zz, $rrrr || $af || 3 || 6*
+
| Zero Page, Relative || BBS2 $zz, $rr || $af || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBS3 $zz, $rrrr || $bf || 3 || 6*
+
| Zero Page, Relative || BBS3 $zz, $rr || $bf || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBS4 $zz, $rrrr || $cf || 3 || 6*
+
| Zero Page, Relative || BBS4 $zz, $rr || $cf || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBS5 $zz, $rrrr || $df || 3 || 6*
+
| Zero Page, Relative || BBS5 $zz, $rr || $df || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBS6 $zz, $rrrr || $ef || 3 || 6*
+
| Zero Page, Relative || BBS6 $zz, $rr || $ef || 3 || 6*
 
|-
 
|-
| Zero Page, Relative || BBS7 $zz, $rrrr || $ff || 3 || 6*
+
| Zero Page, Relative || BBS7 $zz, $rr || $ff || 3 || 6*
 
|}
 
|}
<pre>* Add 2 extra cycles if branch is taken.</pre>
+
[pre]* Add 2 extra cycles if branch is taken.[/pre]
 +
 
 
== BCC - Branch on Carry Clear ==
 
== BCC - Branch on Carry Clear ==
 
{|
 
{|
Line 150: Line 257:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>If the carry flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the carry flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Relative || BCC $rrrr || $90 || 2 || 2(4 if branch taken)
+
| Relative || BCC $rr || $90 || 2 || 2(4 if branch taken)
 
|}
 
|}
 +
 
== BCS - Branch on Carry Set ==
 
== BCS - Branch on Carry Set ==
 
{|
 
{|
Line 166: Line 274:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>If the carry flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the carry flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
<p><br /></p>
+
 
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Relative || BCS $rrrr || $b0 || 2 || 2(4 if branch taken)
+
| Relative || BCS $rr || $b0 || 2 || 2(4 if branch taken)
 
|}
 
|}
 +
 
== BEQ - Branch on Equal(Zero Set) ==
 
== BEQ - Branch on Equal(Zero Set) ==
 
{|
 
{|
Line 183: Line 292:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
<p>If the zero flag is set, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When
+
<p>If the zero flag is set, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
<p><br /></p>
+
 
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Relative || BEQ $rrrr || $f0 || 2 || 2(4 if branch taken)
+
| Relative || BEQ $rr || $f0 || 2 || 2(4 if branch taken)
 
|}
 
|}
 +
 
== BIT - Test Memory Bits with Accumulator ==
 
== BIT - Test Memory Bits with Accumulator ==
 
{|
 
{|
Line 200: Line 310:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || ? || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || ? || 0 || || || ? ||
 
|}
 
|}
 +
 +
<p>Performs an AND between the accumulator and the specified operand without storing the result.
 +
Bit 7 and 6 of the memory operand are respectively saved in the negative (N) and overflow (V) flags.
 +
</p>
 +
 
{|
 
{|
 +
|-
 +
| N || Negative Flag || Bit 7 of M
 +
|-
 +
| V || Overflow Flag || Bit 6 of M
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if A & M == 0
 +
|-
 +
| C || Carry Flag || N/A
 +
|-
 +
|}
 +
 +
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 216: Line 350:
 
| Absolute, X || BIT $aaaa,X || $3c || 3 || 5
 
| Absolute, X || BIT $aaaa,X || $3c || 3 || 5
 
|}
 
|}
 +
 
== BMI - Branch on Minus(Negative Set) ==
 
== BMI - Branch on Minus(Negative Set) ==
 
{|
 
{|
Line 221: Line 356:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>If the negative flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the negative flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
<p><br /></p>
+
 
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Relative || BMI $rrrr || $30 || 2 || 2(4 if branch taken)
+
| Relative || BMI $rr || $30 || 2 || 2(4 if branch taken)
 
|}
 
|}
 +
 
== BNE - Branch on Not Equal(Zero Clear) ==
 
== BNE - Branch on Not Equal(Zero Clear) ==
 
{|
 
{|
Line 238: Line 374:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>If the zero flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the zero flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
<p><br /></p>
+
 
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Relative || BNE $rrrr || $d0 || 2 || 2(4 if branch taken)
+
| Relative || BNE $rr || $d0 || 2 || 2(4 if branch taken)
 
|}
 
|}
 +
 
== BPL - Branch on Plus(Negative Clear) ==
 
== BPL - Branch on Plus(Negative Clear) ==
 
{|
 
{|
Line 255: Line 392:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>If the negative flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the negative flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
<p><br /></p>
+
 
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Relative || BPL $rrrr || $10 || 2 || 2(4 if branch taken)
+
| Relative || BPL $rr || $10 || 2 || 2(4 if branch taken)
 
|}
 
|}
 +
 
== BRA - Branch ==
 
== BRA - Branch ==
 
{|
 
{|
Line 272: Line 410:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Unconditionally branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>Unconditionally branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
<p><br /></p>
+
 
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Relative || BRA $rrrr || $80 || 2 || 4
+
| Relative || BRA $rr || $80 || 2 || 4
 
|}
 
|}
 +
 
== BRK - Break ==
 
== BRK - Break ==
 
{|
 
{|
Line 289: Line 428:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || 0 || 1 || &nbsp; || &nbsp;
+
| || || 0 || 0 || 1 || ||
 
|}
 
|}
 
<p>Forces a software interrupt using [[IRQ2]]'s vector.  Contrary to IRQs, BRK will push the status flags register with bit 4('B' flag) set.</p>
 
<p>Forces a software interrupt using [[IRQ2]]'s vector.  Contrary to IRQs, BRK will push the status flags register with bit 4('B' flag) set.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 298: Line 437:
 
| Implied || BRK || $00 || 1 || 8
 
| Implied || BRK || $00 || 1 || 8
 
|}
 
|}
 +
 
== BSR - Branch to Subroutine ==
 
== BSR - Branch to Subroutine ==
 
{|
 
{|
Line 303: Line 443:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
{|
+
 
 +
The program counter (last byte of the BSR instruction) is pushed to stack and the CPU branches to the specified relative address.
 +
 
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Relative || BSR $rrrr || $44 || 2 || 8
+
| Relative || BSR $rr || $44 || 2 || 8
 
|}
 
|}
 +
 
== BVC - Branch on Overflow Clear ==
 
== BVC - Branch on Overflow Clear ==
 
{|
 
{|
Line 316: Line 460:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>If the overflow flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the overflow flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Relative || BVC $rrrr || $50 || 2 || 2
+
| Relative || BVC $rr || $50 || 2 || 2
 
|}
 
|}
 +
 
== BVS - Branch on Overflow Set ==
 
== BVS - Branch on Overflow Set ==
 
{|
 
{|
Line 332: Line 477:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>If the overflow flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the overflow flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
 
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
|-
 
|-
| Relative || BVS $rrrr || $70 || 2 || 2
+
| Relative || BVS $rr || $70 || 2 || 2
 
|}
 
|}
 +
 
== CLA - Clear Accumulator ==
 
== CLA - Clear Accumulator ==
 
{|
 
{|
Line 348: Line 494:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Clears the accumulator(reset to 0).</p>
 
<p>Clears the accumulator(reset to 0).</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 357: Line 503:
 
| Implied || CLA || $62 || 1 || 2
 
| Implied || CLA || $62 || 1 || 2
 
|}
 
|}
 +
 
== CLC - Clear Carry Flag ==
 
== CLC - Clear Carry Flag ==
 
{|
 
{|
Line 362: Line 509:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || 0
+
| || || 0 || || || || 0
 
|}
 
|}
 
<p>Clears the carry flag.</p>
 
<p>Clears the carry flag.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 371: Line 518:
 
| Implied || CLC || $18 || 1 || 2
 
| Implied || CLC || $18 || 1 || 2
 
|}
 
|}
 +
 
== CLD - Clear Decimal Flag ==
 
== CLD - Clear Decimal Flag ==
 
{|
 
{|
Line 376: Line 524:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || 0 || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || 0 || || ||
 
|}
 
|}
 
<p>Clears the decimal flag, disabling [[Decimal Mode | decimal mode]].</p>
 
<p>Clears the decimal flag, disabling [[Decimal Mode | decimal mode]].</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 385: Line 533:
 
| Implied || CLD || $d8 || 1 || 2
 
| Implied || CLD || $d8 || 1 || 2
 
|}
 
|}
 +
 
== CLI - Clear Interrupt Flag ==
 
== CLI - Clear Interrupt Flag ==
 
{|
 
{|
Line 390: Line 539:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || 0 || &nbsp; || &nbsp;
+
| || || 0 || || 0 || ||
 
|}
 
|}
 
<p>Clears the interrupt flag, allowing IRQs to be processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).</p>
 
<p>Clears the interrupt flag, allowing IRQs to be processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 399: Line 548:
 
| Implied || CLI || $58 || 1 || 2
 
| Implied || CLI || $58 || 1 || 2
 
|}
 
|}
 +
 
== CLV - Clear Overflow Flag ==
 
== CLV - Clear Overflow Flag ==
 
{|
 
{|
Line 404: Line 554:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || 0 || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || 0 || 0 || || || ||
 
|}
 
|}
{|
+
Clears the overflow flag (V).
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 412: Line 563:
 
| Implied || CLV || $b8 || 1 || 2
 
| Implied || CLV || $b8 || 1 || 2
 
|}
 
|}
 +
 
== CLX - Clear X ==
 
== CLX - Clear X ==
 
{|
 
{|
Line 417: Line 569:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
{|
+
Clears the X register.
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 425: Line 578:
 
| Implied || CLX || $82 || 1 || 2
 
| Implied || CLX || $82 || 1 || 2
 
|}
 
|}
 +
 
== CLY - Clear Y ==
 
== CLY - Clear Y ==
 
{|
 
{|
Line 430: Line 584:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
{|
+
Clears the Y register.
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 438: Line 593:
 
| Implied || CLY || $c2 || 1 || 2
 
| Implied || CLY || $c2 || 1 || 2
 
|}
 
|}
 +
 
== CMP - Compare Accumulator with Memory ==
 
== CMP - Compare Accumulator with Memory ==
 
{|
 
{|
Line 443: Line 599:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || ?
+
| ? || || 0 || || || ? || ?
 
|}
 
|}
 +
 +
The content of the operand is subtracted from the accumulator and the status register is set accordingly.
 +
The result of the subtraction is not stored.
 +
 
{|
 
{|
 +
|-
 +
| N || Negative Flag || Set if bit 7 of the result is set
 +
|-
 +
| V || Overflow Flag || N/A
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if A == M
 +
|-
 +
| C || Carry Flag || Set if A >= M
 +
|-
 +
|}
 +
 +
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 461: Line 640:
 
| Absolute, Y || CMP $aaaa,Y || $d9 || 3 || 5
 
| Absolute, Y || CMP $aaaa,Y || $d9 || 3 || 5
 
|-
 
|-
| Indirect || CMP ($zz) || $d2 || 3 || 7
+
| Indirect || CMP ($zzzz) || $d2 || 3 || 7
 
|-
 
|-
 
| Indexed Indirect || CMP ($zz,X) || $c1 || 2 || 7
 
| Indexed Indirect || CMP ($zz,X) || $c1 || 2 || 7
Line 467: Line 646:
 
| Indirect, Index || CMP ($zz),Y || $d1 || 2 || 7
 
| Indirect, Index || CMP ($zz),Y || $d1 || 2 || 7
 
|}
 
|}
 +
 
== CPX - Compare X with Memory ==
 
== CPX - Compare X with Memory ==
 
{|
 
{|
Line 472: Line 652:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || ?
+
| ? || || 0 || || || ? || ?
 
|}
 
|}
 +
 +
The content of the operand is subtracted from the X register and the status register is set accordingly. The result of the subtraction is not stored.
 +
 
{|
 
{|
 +
|-
 +
| N || Negative Flag || Set if bit 7 of the result is set
 +
|-
 +
| V || Overflow Flag || N/A
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if X == M
 +
|-
 +
| C || Carry Flag || Set if X >= M
 +
|-
 +
|}
 +
 +
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 484: Line 686:
 
| Absolute || CPX $aaaa || $ec || 3 || 5
 
| Absolute || CPX $aaaa || $ec || 3 || 5
 
|}
 
|}
 +
 
== CPY - Compare Y with Memory ==
 
== CPY - Compare Y with Memory ==
 
{|
 
{|
Line 489: Line 692:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || ?
+
| ? || || 0 || || || ? || ?
 
|}
 
|}
 +
 +
The content of the operand is subtracted from the Y register and the status register is set accordingly. The result of the subtraction is not stored.
 +
 
{|
 
{|
 +
|-
 +
| N || Negative Flag || Set if bit 7 of the result is set
 +
|-
 +
| V || Overflow Flag || N/A
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if Y == M
 +
|-
 +
| C || Carry Flag || Set if Y >= M
 +
|-
 +
|}
 +
 +
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 500: Line 725:
 
|-
 
|-
 
| Absolute || CPY $aaaa || $cc || 3 || 5
 
| Absolute || CPY $aaaa || $cc || 3 || 5
 
 
|}
 
|}
 +
 
== CSH - Change Speed High ==
 
== CSH - Change Speed High ==
 
{|
 
{|
Line 507: Line 732:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
{|
+
 
 +
Set CPU to high speed mode (7.16 MHz).
 +
 
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 515: Line 743:
 
| Implied || CSH || $d4 || 1 || 3
 
| Implied || CSH || $d4 || 1 || 3
 
|}
 
|}
 +
 
== CSL - Change Speed Low ==
 
== CSL - Change Speed Low ==
 
{|
 
{|
Line 520: Line 749:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
{|
+
 
 +
Set CPU to low speed mode (1.78 MHz).
 +
 
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 528: Line 760:
 
| Implied || CSL || $54 || 1 || 3
 
| Implied || CSL || $54 || 1 || 3
 
|}
 
|}
 +
 
== DEC - Decrement ==
 
== DEC - Decrement ==
 
{|
 
{|
Line 533: Line 766:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 +
 +
Decrement the operand by 1.
 +
 
{|
 
{|
 +
|-
 +
| N || Negative Flag || Set if bit 7 of the result is set
 +
|-
 +
| V || Overflow Flag || N/A
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if the result is zero
 +
|-
 +
| C || Carry Flag || N/A
 +
|-
 +
|}
 +
 +
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 547: Line 802:
 
| Absolute, X || DEC $aaaa,X || $de || 3 || 7
 
| Absolute, X || DEC $aaaa,X || $de || 3 || 7
 
|}
 
|}
 +
 
== DEX - Decrement X ==
 
== DEX - Decrement X ==
 
{|
 
{|
Line 552: Line 808:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 +
 +
Decrement the X register by 1.
 +
 
{|
 
{|
 +
|-
 +
| N || Negative Flag || Set if bit 7 of the X register is set
 +
|-
 +
| V || Overflow Flag || N/A
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if the X register is zero
 +
|-
 +
| C || Carry Flag || N/A
 +
|-
 +
|}
 +
 +
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 560: Line 838:
 
| Implied || DEX || $ca || 1 || 2
 
| Implied || DEX || $ca || 1 || 2
 
|}
 
|}
 +
 
== DEY - Decrement Y ==
 
== DEY - Decrement Y ==
 
{|
 
{|
Line 565: Line 844:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 +
 +
Decrement the Y register by 1.
 +
 
{|
 
{|
 +
|-
 +
| N || Negative Flag || Set if bit 7 of the Y register is set
 +
|-
 +
| V || Overflow Flag || N/A
 +
|-
 +
| T || T Flag || 0
 +
|-
 +
| D || Decimal Flag || N/A
 +
|-
 +
| I || Interrupt Disable || N/A
 +
|-
 +
| Z || Zero Flag || Set if the Y register is zero
 +
|-
 +
| C || Carry Flag || N/A
 +
|-
 +
|}
 +
 +
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 573: Line 874:
 
| Implied || DEY || $88 || 1 || 2
 
| Implied || DEY || $88 || 1 || 2
 
|}
 
|}
 +
 
== EOR - Exclusive OR Accumulator with Memory ==
 
== EOR - Exclusive OR Accumulator with Memory ==
 
{|
 
{|
Line 578: Line 880:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Logically [[XOR]] the value referenced by the operand to the accumulator.</p>
 
<p>Logically [[XOR]] the value referenced by the operand to the accumulator.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 597: Line 899:
 
| Absolute, Y || EOR $aaaa,Y || $59 || 3 || 5
 
| Absolute, Y || EOR $aaaa,Y || $59 || 3 || 5
 
|-
 
|-
| Indirect || EOR ($zz) || $52 || 3 || 7
+
| Indirect || EOR ($zzzz) || $52 || 3 || 7
 
|-
 
|-
 
| Indexed Indirect || EOR ($zz,X) || $41 || 2 || 7
 
| Indexed Indirect || EOR ($zz,X) || $41 || 2 || 7
Line 603: Line 905:
 
| Indirect, Index || EOR ($zz),Y || $51 || 2 || 7
 
| Indirect, Index || EOR ($zz),Y || $51 || 2 || 7
 
|}
 
|}
 +
 
== INC - Increment ==
 
== INC - Increment ==
 
{|
 
{|
Line 608: Line 911:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Increments the value of the location specified by the operand by one.  The Carry flag is not used, nor is it modified.</p>
 
<p>Increments the value of the location specified by the operand by one.  The Carry flag is not used, nor is it modified.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 625: Line 928:
 
| Absolute, X || INC $aaaa,X || $fe || 3 || 7
 
| Absolute, X || INC $aaaa,X || $fe || 3 || 7
 
|}
 
|}
 +
 
== INX - Increment X ==
 
== INX - Increment X ==
 
{|
 
{|
Line 630: Line 934:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Increments the value in the X register by one.  The Carry flag is not used, nor is it modified.</p>
 
<p>Increments the value in the X register by one.  The Carry flag is not used, nor is it modified.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 639: Line 943:
 
| Implied || INX || $e8 || 1 || 2
 
| Implied || INX || $e8 || 1 || 2
 
|}
 
|}
 +
 
== INY - Increment Y ==
 
== INY - Increment Y ==
 
{|
 
{|
Line 644: Line 949:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Increments the value in the Y register by one.  The Carry flag is not used, nor is it modified.</p>
 
<p>Increments the value in the Y register by one.  The Carry flag is not used, nor is it modified.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 653: Line 958:
 
| Implied || INY || $c8 || 1 || 2
 
| Implied || INY || $c8 || 1 || 2
 
|}
 
|}
 +
 
== JMP - Jump ==
 
== JMP - Jump ==
 
{|
 
{|
Line 658: Line 964:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Transfers control(sets the program counter) to the effective address calculated from the operand.</p>
 
<p>Transfers control(sets the program counter) to the effective address calculated from the operand.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 667: Line 973:
 
| Absolute || JMP $aaaa || $4c || 3 || 4
 
| Absolute || JMP $aaaa || $4c || 3 || 4
 
|-
 
|-
| Indirect || JMP ($aaaa) || $6c || 3 || 7
+
| Indirect || JMP ($zzzz) || $6c || 3 || 7
 
|-
 
|-
| Indexed Indirect || JMP ($aaaa,X) || $7c || 3 || 7
+
| Indexed Indirect || JMP ($zzzz,X) || $7c || 3 || 7
 
|}
 
|}
 +
 
== JSR - Jump to Subroutine ==
 
== JSR - Jump to Subroutine ==
 
{|
 
{|
Line 676: Line 983:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
{|
+
 
 +
Push the current program counter value (minus 1) onto the stack and set it to the address specified in the second operand.
 +
 
 +
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 684: Line 994:
 
| Absolute || JSR $aaaa || $20 || 3 || 7
 
| Absolute || JSR $aaaa || $20 || 3 || 7
 
|}
 
|}
 +
 
== LDA - Load Accumulator ==
 
== LDA - Load Accumulator ==
 
{|
 
{|
Line 689: Line 1,000:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Loads the accumulator with the value at the effective address.</p>
 
<p>Loads the accumulator with the value at the effective address.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 708: Line 1,019:
 
| Absolute, Y || LDA $aaaa,Y || $b9 || 3 || 5
 
| Absolute, Y || LDA $aaaa,Y || $b9 || 3 || 5
 
|-
 
|-
| Indirect || LDA ($zz) || $b2 || 3 || 7
+
| Indirect || LDA ($zzzz) || $b2 || 3 || 7
 
|-
 
|-
 
| Indexed Indirect || LDA ($zz,X) || $a1 || 2 || 7
 
| Indexed Indirect || LDA ($zz,X) || $a1 || 2 || 7
Line 714: Line 1,025:
 
| Indirect, Index || LDA ($zz),Y || $b1 || 2 || 7
 
| Indirect, Index || LDA ($zz),Y || $b1 || 2 || 7
 
|}
 
|}
 +
 
== LDX - Load X ==
 
== LDX - Load X ==
 
{|
 
{|
Line 719: Line 1,031:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Loads the X register with the value at the effective address.</p>
 
<p>Loads the X register with the value at the effective address.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 736: Line 1,048:
 
| Absolute, Y || LDX $aaaa,Y || $be || 3 || 5
 
| Absolute, Y || LDX $aaaa,Y || $be || 3 || 5
 
|}
 
|}
 +
 
== LDY - Load Y ==
 
== LDY - Load Y ==
 
{|
 
{|
Line 741: Line 1,054:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Loads the Y register with the value at the effective address.</p>
 
<p>Loads the Y register with the value at the effective address.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 758: Line 1,071:
 
| Absolute, X || LDY $aaaa,X || $bc || 3 || 5
 
| Absolute, X || LDY $aaaa,X || $bc || 3 || 5
 
|}
 
|}
 +
 
== LSR - Logical Shift Right ==
 
== LSR - Logical Shift Right ==
 
{|
 
{|
Line 763: Line 1,077:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || 0
+
| ? || || 0 || || || ? || 0
 
|}
 
|}
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 779: Line 1,093:
 
| Absolute, X || LSR $aaaa,X || $5e || 3 || 7
 
| Absolute, X || LSR $aaaa,X || $5e || 3 || 7
 
|}
 
|}
 +
 
== NOP - No Operation ==
 
== NOP - No Operation ==
 
{|
 
{|
Line 784: Line 1,099:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 792: Line 1,107:
 
| Implied || NOP || $ea || 1 || 2
 
| Implied || NOP || $ea || 1 || 2
 
|}
 
|}
 +
 
== ORA - OR Accumulator with Memory ==
 
== ORA - OR Accumulator with Memory ==
 
{|
 
{|
Line 797: Line 1,113:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Logically [[OR]] the value referenced by the operand with the accumulator, storing the result in the accumulator.</p>
 
<p>Logically [[OR]] the value referenced by the operand with the accumulator, storing the result in the accumulator.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 816: Line 1,132:
 
| Absolute, Y || ORA $aaaa,Y || $19 || 3 || 5
 
| Absolute, Y || ORA $aaaa,Y || $19 || 3 || 5
 
|-
 
|-
| Indirect || ORA ($zz) || $12 || 3 || 7
+
| Indirect || ORA ($zzzz) || $12 || 3 || 7
 
|-
 
|-
 
| Indexed Indirect || ORA ($zz,X) || $01 || 2 || 7
 
| Indexed Indirect || ORA ($zz,X) || $01 || 2 || 7
Line 822: Line 1,138:
 
| Indirect, Index || ORA ($zz),Y || $11 || 2 || 7
 
| Indirect, Index || ORA ($zz),Y || $11 || 2 || 7
 
|}
 
|}
 +
 
== PHA - Push A ==
 
== PHA - Push A ==
 
{|
 
{|
Line 827: Line 1,144:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Pushes the accumulator to the stack.</p>
 
<p>Pushes the accumulator to the stack.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 836: Line 1,153:
 
| Implied || PHA || $48 || 1 || 3
 
| Implied || PHA || $48 || 1 || 3
 
|}
 
|}
 +
 
== PHP - Push P ==
 
== PHP - Push P ==
 
{|
 
{|
Line 841: Line 1,159:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Pushes the status flags(1 byte) to the stack.</p>
 
<p>Pushes the status flags(1 byte) to the stack.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 850: Line 1,168:
 
| Implied || PHP || $08 || 1 || 3
 
| Implied || PHP || $08 || 1 || 3
 
|}
 
|}
 +
 
== PHX - Push X ==
 
== PHX - Push X ==
 
{|
 
{|
Line 855: Line 1,174:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Pushes the X register to the stack.</p>
 
<p>Pushes the X register to the stack.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 864: Line 1,183:
 
| Implied || PHX || $da || 1 || 3
 
| Implied || PHX || $da || 1 || 3
 
|}
 
|}
 +
 
== PHY - Push Y ==
 
== PHY - Push Y ==
 
{|
 
{|
Line 869: Line 1,189:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Pushes the Y register to the stack.</p>
 
<p>Pushes the Y register to the stack.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 878: Line 1,198:
 
| Implied || PHY || $5a || 1 || 3
 
| Implied || PHY || $5a || 1 || 3
 
|}
 
|}
 +
 
== PLA - Pull A ==
 
== PLA - Pull A ==
 
{|
 
{|
Line 883: Line 1,204:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Pulls a value off the stack, and stores the value in the accumulator.</p>
 
<p>Pulls a value off the stack, and stores the value in the accumulator.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 892: Line 1,213:
 
| Implied || PLA || $68 || 1 || 4
 
| Implied || PLA || $68 || 1 || 4
 
|}
 
|}
 +
 
== PLP - Pull P ==
 
== PLP - Pull P ==
 
{|
 
{|
Line 899: Line 1,221:
 
| ? || ? || ? || ? || ? || ? || ?
 
| ? || ? || ? || ? || ? || ? || ?
 
|}
 
|}
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 905: Line 1,227:
 
| Implied || PLP || $28 || 1 || 4
 
| Implied || PLP || $28 || 1 || 4
 
|}
 
|}
<p><br /></p>
+
 
 
== PLX - Pull X ==
 
== PLX - Pull X ==
 
{|
 
{|
Line 911: Line 1,233:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Pulls a value off the stack, and stores the value in the X register.</p>
 
<p>Pulls a value off the stack, and stores the value in the X register.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 920: Line 1,242:
 
| Implied || PLX || $fa || 1 || 4
 
| Implied || PLX || $fa || 1 || 4
 
|}
 
|}
 +
 
== PLY - Pull Y ==
 
== PLY - Pull Y ==
 
{|
 
{|
Line 925: Line 1,248:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Pulls a value off the stack, and stores the value in Y register.</p>
 
<p>Pulls a value off the stack, and stores the value in Y register.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 934: Line 1,257:
 
| Implied || PLY || $7a || 1 || 4
 
| Implied || PLY || $7a || 1 || 4
 
|}
 
|}
 +
 
== RMBn - Reset Memory Bit n ==
 
== RMBn - Reset Memory Bit n ==
 
{|
 
{|
Line 939: Line 1,263:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Reads the zero-page address specified by the operand, resets(clears) the bit "n", and then writes it back to the aforementioned address.</p>
 
<p>Reads the zero-page address specified by the operand, resets(clears) the bit "n", and then writes it back to the aforementioned address.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 962: Line 1,286:
 
| Zero Page || RMB7 $zz || $77 || 2 || 7
 
| Zero Page || RMB7 $zz || $77 || 2 || 7
 
|}
 
|}
 +
 
== ROL - Rotate Left ==
 
== ROL - Rotate Left ==
 
{|
 
{|
Line 967: Line 1,292:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || ?
+
| ? || || 0 || || || ? || ?
 
|}
 
|}
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 983: Line 1,308:
 
| Absolute, X || ROL $aaaa,X || $3e || 3 || 7
 
| Absolute, X || ROL $aaaa,X || $3e || 3 || 7
 
|}
 
|}
 +
 
== ROR - Rotate Right ==
 
== ROR - Rotate Right ==
 
{|
 
{|
Line 988: Line 1,314:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || ?
+
| ? || || 0 || || || ? || ?
 
|}
 
|}
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,004: Line 1,330:
 
| Absolute, X || ROR $aaaa,X || $7e || 3 || 7
 
| Absolute, X || ROR $aaaa,X || $7e || 3 || 7
 
|}
 
|}
 +
 
== RTI - Return from Interrupt ==
 
== RTI - Return from Interrupt ==
 
{|
 
{|
Line 1,011: Line 1,338:
 
| ? || ? || ? || ? || ? || ? || ?
 
| ? || ? || ? || ? || ? || ? || ?
 
|}
 
|}
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,017: Line 1,344:
 
| Implied || RTI || $40 || 1 || 7
 
| Implied || RTI || $40 || 1 || 7
 
|}
 
|}
<p><br /></p>
+
 
 
== RTS - Return from Subroutine ==
 
== RTS - Return from Subroutine ==
 
{|
 
{|
Line 1,023: Line 1,350:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,031: Line 1,358:
 
| Implied || RTS || $60 || 1 || 7
 
| Implied || RTS || $60 || 1 || 7
 
|}
 
|}
<p><br /></p>
+
 
 
== SAX - Swap A and X ==
 
== SAX - Swap A and X ==
 
{|
 
{|
Line 1,037: Line 1,364:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Swaps the values in the accumulator and X register.</p>
 
<p>Swaps the values in the accumulator and X register.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,046: Line 1,373:
 
| Implied || SAX || $22 || 1 || 3
 
| Implied || SAX || $22 || 1 || 3
 
|}
 
|}
 +
 
== SAY - Swap A and Y ==
 
== SAY - Swap A and Y ==
 
{|
 
{|
Line 1,051: Line 1,379:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Swap the values in the accumulator and Y register.</p>
 
<p>Swap the values in the accumulator and Y register.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,060: Line 1,388:
 
| Implied || SAY || $42 || 1 || 3
 
| Implied || SAY || $42 || 1 || 3
 
|}
 
|}
 +
 
== SBC - Subtract with Borrow ==
 
== SBC - Subtract with Borrow ==
 
{|
 
{|
Line 1,065: Line 1,394:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || ? || 0 || &nbsp; || &nbsp; || ? || ?
+
| ? || ? || 0 || || || ? || ?
 
|}
 
|}
 
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).</p>
 
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).</p>
 
<p>The overflow flag is not affected by this instruction if in Decimal mode.</p>
 
<p>The overflow flag is not affected by this instruction if in Decimal mode.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,085: Line 1,414:
 
| Absolute, Y || SBC $aaaa,Y || $f9 || 3 || 5
 
| Absolute, Y || SBC $aaaa,Y || $f9 || 3 || 5
 
|-
 
|-
| Indirect || SBC ($zz) || $f2 || 3 || 7
+
| Indirect || SBC ($zzzz) || $f2 || 3 || 7
 
|-
 
|-
 
| Indexed Indirect || SBC ($zz,X) || $e1 || 2 || 7
 
| Indexed Indirect || SBC ($zz,X) || $e1 || 2 || 7
Line 1,091: Line 1,420:
 
| Indirect, Index || SBC ($zz),Y || $f1 || 2 || 7
 
| Indirect, Index || SBC ($zz),Y || $f1 || 2 || 7
 
|}
 
|}
 +
 
== SEC - Set Carry Flag ==
 
== SEC - Set Carry Flag ==
 
{|
 
{|
Line 1,096: Line 1,426:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || 1
+
| || || 0 || || || || 1
 
|}
 
|}
 
<p>Sets the carry flag.</p>
 
<p>Sets the carry flag.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,105: Line 1,435:
 
| Implied || SEC || $38 || 1 || 2
 
| Implied || SEC || $38 || 1 || 2
 
|}
 
|}
 +
 
== SED - Set Decimal Flag ==
 
== SED - Set Decimal Flag ==
 
{|
 
{|
Line 1,110: Line 1,441:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || 1 || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || 1 || || ||
 
|}
 
|}
 
<p>Sets the decimal flag, enabling [[Decimal Mode | decimal mode]].</p>
 
<p>Sets the decimal flag, enabling [[Decimal Mode | decimal mode]].</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,119: Line 1,450:
 
| Implied || SED || $f8 || 1 || 2
 
| Implied || SED || $f8 || 1 || 2
 
|}
 
|}
 +
 
== SEI - Set Interrupt Flag ==
 
== SEI - Set Interrupt Flag ==
 
{|
 
{|
Line 1,124: Line 1,456:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || 1 || &nbsp; || &nbsp;
+
| || || 0 || || 1 || ||
 
|}
 
|}
 
<p>Sets the interrupt flag, preventing IRQs from being processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).</p>
 
<p>Sets the interrupt flag, preventing IRQs from being processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,133: Line 1,465:
 
| Implied || SEI || $78 || 1 || 2
 
| Implied || SEI || $78 || 1 || 2
 
|}
 
|}
 +
 
== SET - Set T Flag ==
 
== SET - Set T Flag ==
 
{|
 
{|
Line 1,138: Line 1,471:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 1 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 1 || || || ||
 
|}
 
|}
 
<p>Sets the T flag, which changes the behavior of the next instruction if the next instruction is ADC, AND, EOR, ORA, or SBC, in which case the operation is performed on the zero-page address specified by the X register, instead of the accumulator.</p>
 
<p>Sets the T flag, which changes the behavior of the next instruction if the next instruction is ADC, AND, EOR, ORA, or SBC, in which case the operation is performed on the zero-page address specified by the X register, instead of the accumulator.</p>
 
<p>Note that interrupt processing preserves the T-flag, and clears the T-flag in the interrupt handler, so a programmer needn't worry about an interrupt
 
<p>Note that interrupt processing preserves the T-flag, and clears the T-flag in the interrupt handler, so a programmer needn't worry about an interrupt
 
occuring between SET and the next instruction.</p>
 
occuring between SET and the next instruction.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,149: Line 1,482:
 
| Implied || SET || $f4 || 1 || 2
 
| Implied || SET || $f4 || 1 || 2
 
|}
 
|}
 +
 
== SMBn - Set Memory Bit n ==
 
== SMBn - Set Memory Bit n ==
 
{|
 
{|
Line 1,154: Line 1,488:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Reads the zero-page address specified by the operand, sets the bit "n", and then writes it back to the aforementioned address.</p>
 
<p>Reads the zero-page address specified by the operand, sets the bit "n", and then writes it back to the aforementioned address.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,176: Line 1,510:
 
|-
 
|-
 
| Zero Page || SMB7 $zz || $f7 || 2 || 7
 
| Zero Page || SMB7 $zz || $f7 || 2 || 7
 +
|}
  
|}
 
 
== ST0 - Store [[HuC6270 | (HuC6270) VDC]] No. 0 ==
 
== ST0 - Store [[HuC6270 | (HuC6270) VDC]] No. 0 ==
 
{|
 
{|
Line 1,183: Line 1,517:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Writes the immediate value to the physical address $1FE000, the [[HuC6270 | (HuC6270) VDC]]'s address register.</p>
 
<p>Writes the immediate value to the physical address $1FE000, the [[HuC6270 | (HuC6270) VDC]]'s address register.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,192: Line 1,526:
 
| Immediate || ST0 #$ii || $03 || 2 || 5
 
| Immediate || ST0 #$ii || $03 || 2 || 5
 
|}
 
|}
 +
 
== ST1 - Store [[HuC6270 | (HuC6270) VDC]] No. 1 ==
 
== ST1 - Store [[HuC6270 | (HuC6270) VDC]] No. 1 ==
 
{|
 
{|
Line 1,197: Line 1,532:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Writes the immediate value to the physical address $1FE002, the [[HuC6270 | (HuC6270) VDC]]'s lower data register.</p>
 
<p>Writes the immediate value to the physical address $1FE002, the [[HuC6270 | (HuC6270) VDC]]'s lower data register.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,206: Line 1,541:
 
| Immediate || ST1 #$ii || $13 || 2 || 5
 
| Immediate || ST1 #$ii || $13 || 2 || 5
 
|}
 
|}
 +
 
== ST2 - Store [[HuC6270 | (HuC6270) VDC]] No. 2 ==
 
== ST2 - Store [[HuC6270 | (HuC6270) VDC]] No. 2 ==
 
{|
 
{|
Line 1,211: Line 1,547:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Writes the immediate value to the physical address $1FE003, the [[HuC6270 | (HuC6270) VDC]]'s upper data register.</p>
 
<p>Writes the immediate value to the physical address $1FE003, the [[HuC6270 | (HuC6270) VDC]]'s upper data register.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,220: Line 1,556:
 
| Immediate || ST2 #$ii || $23 || 2 || 5
 
| Immediate || ST2 #$ii || $23 || 2 || 5
 
|}
 
|}
 +
 
== STA - Store Accumulator ==
 
== STA - Store Accumulator ==
 
{|
 
{|
Line 1,225: Line 1,562:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Stores the value in the accumulator to the effective address specified by the operand.</p>
 
<p>Stores the value in the accumulator to the effective address specified by the operand.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,242: Line 1,579:
 
| Absolute, Y || STA $aaaa,Y || $99 || 3 || 5
 
| Absolute, Y || STA $aaaa,Y || $99 || 3 || 5
 
|-
 
|-
| Indirect || STA ($zz) || $92 || 3 || 7
+
| Indirect || STA ($zzzz) || $92 || 3 || 7
 
|-
 
|-
 
| Indexed Indirect || STA ($zz,X) || $81 || 2 || 7
 
| Indexed Indirect || STA ($zz,X) || $81 || 2 || 7
Line 1,248: Line 1,585:
 
| Indirect, Index || STA ($zz),Y || $91 || 2 || 7
 
| Indirect, Index || STA ($zz),Y || $91 || 2 || 7
 
|}
 
|}
 +
 
== STX - Store X ==
 
== STX - Store X ==
 
{|
 
{|
Line 1,253: Line 1,591:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Stores the value in the X register to the effective address specified by the operand.</p>
 
<p>Stores the value in the X register to the effective address specified by the operand.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,266: Line 1,604:
 
| Absolute || STX $aaaa || $8e || 3 || 5
 
| Absolute || STX $aaaa || $8e || 3 || 5
 
|}
 
|}
 +
 
== STY - Store Y ==
 
== STY - Store Y ==
 
{|
 
{|
Line 1,271: Line 1,610:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Stores the value in the Y register to the effective address specified by the operand.</p>
 
<p>Stores the value in the Y register to the effective address specified by the operand.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,284: Line 1,623:
 
| Absolute || STY $aaaa || $8c || 3 || 5
 
| Absolute || STY $aaaa || $8c || 3 || 5
 
|}
 
|}
 +
 
== STZ - Store Zero ==
 
== STZ - Store Zero ==
 
{|
 
{|
Line 1,289: Line 1,629:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Stores zero to the effective address specified by the operand.</p>
 
<p>Stores zero to the effective address specified by the operand.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,304: Line 1,644:
 
| Absolute, X || STZ $aaaa,X || $9e || 3 || 5
 
| Absolute, X || STZ $aaaa,X || $9e || 3 || 5
 
|}
 
|}
 +
 
== SXY - Swap X and Y ==
 
== SXY - Swap X and Y ==
 
{|
 
{|
Line 1,309: Line 1,650:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Swaps the values in the X register and the Y register.</p>
 
<p>Swaps the values in the X register and the Y register.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,318: Line 1,659:
 
| Implied || SXY || $02 || 1 || 3
 
| Implied || SXY || $02 || 1 || 3
 
|}
 
|}
 +
 
== TAI - Transfer Alternate Increment ==
 
== TAI - Transfer Alternate Increment ==
 
{|
 
{|
Line 1,323: Line 1,665:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
 
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
Line 1,333: Line 1,675:
 
  llll = llll - 1
 
  llll = llll - 1
 
  Alternate = Alternate ^ 1
 
  Alternate = Alternate ^ 1
While llll&nbsp;!= 0</pre>
+
While llll != 0</pre>
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
will be effectively treated as a length of "65536".</p>
 
will be effectively treated as a length of "65536".</p>
Line 1,339: Line 1,681:
 
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer
 
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer
 
is complete.</p>
 
is complete.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,345: Line 1,687:
 
| Block Transfer || TAI $ssss, $dddd, $llll || $f3 || 7 || 17 + 6 * llll
 
| Block Transfer || TAI $ssss, $dddd, $llll || $f3 || 7 || 17 + 6 * llll
 
|}
 
|}
 +
 
== TAM - Transfer Accumulator to [[MPR | MPRs]] ==
 
== TAM - Transfer Accumulator to [[MPR | MPRs]] ==
 
{|
 
{|
Line 1,350: Line 1,693:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Copies the value in the accumulator to each MPR with the corresponding bit set in the immediate operand, eg. TAM #$41 will load MPR0 and MPR6 with the
 
<p>Copies the value in the accumulator to each MPR with the corresponding bit set in the immediate operand, eg. TAM #$41 will load MPR0 and MPR6 with the
 
value in the accumulator.  If no bits are set, no transfer will occur, and the instruction is effectively a 5-cycle NOP.</p>
 
value in the accumulator.  If no bits are set, no transfer will occur, and the instruction is effectively a 5-cycle NOP.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,360: Line 1,703:
 
| Immediate || TAM #$ii || $53 || 2 || 5
 
| Immediate || TAM #$ii || $53 || 2 || 5
 
|}
 
|}
 +
 
== TAX - Transfer Accumulator to X ==
 
== TAX - Transfer Accumulator to X ==
 
{|
 
{|
Line 1,365: Line 1,709:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Copies the value of the accumulator to the X register.</p>
 
<p>Copies the value of the accumulator to the X register.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,374: Line 1,718:
 
| Implied || TAX || $aa || 1 || 2
 
| Implied || TAX || $aa || 1 || 2
 
|}
 
|}
 +
 
== TAY - Transfer Accumulator to Y ==
 
== TAY - Transfer Accumulator to Y ==
 
{|
 
{|
Line 1,379: Line 1,724:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Copies the value of the accumulator to the Y register.</p>
 
<p>Copies the value of the accumulator to the Y register.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,388: Line 1,733:
 
| Implied || TAY || $a8 || 1 || 2
 
| Implied || TAY || $a8 || 1 || 2
 
|}
 
|}
 +
 
== TDD - Transfer Decrement Decrement ==
 
== TDD - Transfer Decrement Decrement ==
 
{|
 
{|
Line 1,393: Line 1,739:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
 
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
Line 1,402: Line 1,748:
 
  dddd = dddd - 1
 
  dddd = dddd - 1
 
  llll = llll - 1
 
  llll = llll - 1
While llll&nbsp;!= 0</pre>
+
While llll != 0</pre>
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
will be effectively treated as a length of "65536".</p>
 
will be effectively treated as a length of "65536".</p>
 
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
 
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
 
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
 
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,413: Line 1,759:
 
| Block Transfer || TDD $ssss, $dddd, $llll || $c3 || 7 || 17 + 6 * llll
 
| Block Transfer || TDD $ssss, $dddd, $llll || $c3 || 7 || 17 + 6 * llll
 
|}
 
|}
 +
 
== TIA - Transfer Increment Alternate ==
 
== TIA - Transfer Increment Alternate ==
 
{|
 
{|
Line 1,418: Line 1,765:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p><br />
 
<p><br />
Line 1,429: Line 1,776:
 
  llll = llll - 1
 
  llll = llll - 1
 
  Alternate = Alternate ^ 1
 
  Alternate = Alternate ^ 1
While llll&nbsp;!= 0</pre>
+
While llll != 0</pre>
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
will be effectively treated as a length of "65536".</p>
 
will be effectively treated as a length of "65536".</p>
 
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
 
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
 
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
 
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,440: Line 1,787:
 
| Block Transfer || TIA $ssss, $dddd, $llll || $e3 || 7 || 17 + 6 * llll
 
| Block Transfer || TIA $ssss, $dddd, $llll || $e3 || 7 || 17 + 6 * llll
 
|}
 
|}
 +
 
== TII - Transfer Increment Increment ==
 
== TII - Transfer Increment Increment ==
 
{|
 
{|
Line 1,445: Line 1,793:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
 
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
Line 1,454: Line 1,802:
 
  dddd = dddd + 1
 
  dddd = dddd + 1
 
  llll = llll - 1
 
  llll = llll - 1
While llll&nbsp;!= 0</pre>
+
While llll != 0</pre>
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
will be effectively treated as a length of "65536".</p>
 
will be effectively treated as a length of "65536".</p>
 
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
 
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
 
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
 
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,465: Line 1,813:
 
| Block Transfer || TII $ssss, $dddd, $llll || $73 || 7 || 17 + 6 * llll
 
| Block Transfer || TII $ssss, $dddd, $llll || $73 || 7 || 17 + 6 * llll
 
|}
 
|}
 +
 
== TIN - Transfer Increment ==
 
== TIN - Transfer Increment ==
 
{|
 
{|
Line 1,470: Line 1,819:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
 
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
Line 1,478: Line 1,827:
 
  ssss = ssss + 1
 
  ssss = ssss + 1
 
  llll = llll - 1
 
  llll = llll - 1
While llll&nbsp;!= 0</pre>
+
While llll != 0</pre>
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
will be effectively treated as a length of "65536".</p>
 
will be effectively treated as a length of "65536".</p>
 
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
 
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
 
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
 
<p>Please note that the cycles-per-byte-transferred will be higher if [[HuC6270 | (HuC6270) VDC]] registers are used as source and/or destination.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,489: Line 1,838:
 
| Block Transfer || TIN $ssss, $dddd, $llll || $d3 || 7 || 17 + 6 * llll
 
| Block Transfer || TIN $ssss, $dddd, $llll || $d3 || 7 || 17 + 6 * llll
 
|}
 
|}
 +
 
== TMA - Transfer MPR to Accumulator ==
 
== TMA - Transfer MPR to Accumulator ==
 
{|
 
{|
Line 1,494: Line 1,844:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Copies the value in the MPR, specified by the corresponding bit being set in the immediate operand, to the accumulator.  If an immediate value of $00 is used, the accumulator will be loaded with the last value transfered by TAM(note that if an immediate value of $00 is used with TAM, no transfer occurs, and as such won't be read back if an immediate value of $00 is used with TMA).  Undefined behavior results if multiple bits are set.</p>
 
<p>Copies the value in the MPR, specified by the corresponding bit being set in the immediate operand, to the accumulator.  If an immediate value of $00 is used, the accumulator will be loaded with the last value transfered by TAM(note that if an immediate value of $00 is used with TAM, no transfer occurs, and as such won't be read back if an immediate value of $00 is used with TMA).  Undefined behavior results if multiple bits are set.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,503: Line 1,853:
 
| Immediate || TMA #$ii || $43 || 2 || 4
 
| Immediate || TMA #$ii || $43 || 2 || 4
 
|}
 
|}
 +
 
== TRB - Test and Reset Bits against Accumulator ==
 
== TRB - Test and Reset Bits against Accumulator ==
 
{|
 
{|
Line 1,508: Line 1,859:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || ? || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || ? || 0 || || || ? ||
 
|}
 
|}
 
<p>Loads the value specified by the effective address of the operand, clears all bits whose corresponding bits are set in the accumulator(result = value &amp; ~accumulator), and stores the result to the aforementioned address.</p>
 
<p>Loads the value specified by the effective address of the operand, clears all bits whose corresponding bits are set in the accumulator(result = value &amp; ~accumulator), and stores the result to the aforementioned address.</p>
 
<p>The zero flag is set according to the result.  The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address, before it is operated on.</p>
 
<p>The zero flag is set according to the result.  The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address, before it is operated on.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,520: Line 1,871:
 
| Absolute || TRB $aaaa || $1c || 3 || 7
 
| Absolute || TRB $aaaa || $1c || 3 || 7
 
|}
 
|}
 +
 
== TSB - Test and Set Bits against Accumulator ==
 
== TSB - Test and Set Bits against Accumulator ==
 
{|
 
{|
Line 1,525: Line 1,877:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || ? || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || ? || 0 || || || ? ||
 
|}
 
|}
 
<p>Loads the value specified by the effective address of the operand, sets all bits whose corresponding bits are set in the accumulator(result = value &amp; ~accumulator), and stores the result to the aforementioned address.</p>
 
<p>Loads the value specified by the effective address of the operand, sets all bits whose corresponding bits are set in the accumulator(result = value &amp; ~accumulator), and stores the result to the aforementioned address.</p>
 
<p>The zero flag is set according to the result.  The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address, before it is operated on.</p>
 
<p>The zero flag is set according to the result.  The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address, before it is operated on.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,537: Line 1,889:
 
| Absolute || TSB $aaaa || $0c || 3 || 7
 
| Absolute || TSB $aaaa || $0c || 3 || 7
 
|}
 
|}
 +
 
== TST - Test ==
 
== TST - Test ==
 
{|
 
{|
Line 1,542: Line 1,895:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || ? || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || ? || 0 || || || ? ||
 
|}
 
|}
 
<p>The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address(they are *not* set as the result of
 
<p>The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address(they are *not* set as the result of
 
the [[AND]] operation used to determine the Z flag's state).</p>
 
the [[AND]] operation used to determine the Z flag's state).</p>
 
<p>The Z flag is determined according to the result of logically [[AND]]'ing the immediate value and the value at the effective address.</p>
 
<p>The Z flag is determined according to the result of logically [[AND]]'ing the immediate value and the value at the effective address.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,559: Line 1,912:
 
| Immediate, Absolute, X || TST #$ii, $aaaa, X || $b3 || 4 || 8
 
| Immediate, Absolute, X || TST #$ii, $aaaa, X || $b3 || 4 || 8
 
|}
 
|}
 +
 
== TSX - Transfer Stack Pointer to X ==
 
== TSX - Transfer Stack Pointer to X ==
 
{|
 
{|
Line 1,564: Line 1,918:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,572: Line 1,926:
 
| Implied || TSX || $ba || 1 || 2
 
| Implied || TSX || $ba || 1 || 2
 
|}
 
|}
 +
 
== TXA - Transfer X to A ==
 
== TXA - Transfer X to A ==
 
{|
 
{|
Line 1,577: Line 1,932:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Copies the value in the X register to the Accumulator.</p>
 
<p>Copies the value in the X register to the Accumulator.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,586: Line 1,941:
 
| Implied || TXA || $8a || 1 || 2
 
| Implied || TXA || $8a || 1 || 2
 
|}
 
|}
 +
 
== TXS - Track X to Stack Pointer ==
 
== TXS - Track X to Stack Pointer ==
 
{|
 
{|
Line 1,591: Line 1,947:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| &nbsp; || &nbsp; || 0 || &nbsp; || &nbsp; || &nbsp; || &nbsp;
+
| || || 0 || || || ||
 
|}
 
|}
 
<p>Copies the value in X to the [[Stack Pointer | stack pointer]].</p>
 
<p>Copies the value in X to the [[Stack Pointer | stack pointer]].</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
Line 1,600: Line 1,956:
 
| Implied || TXS || $9a || 1 || 2
 
| Implied || TXS || $9a || 1 || 2
 
|}
 
|}
 +
 
== TYA - Transfer Y to Accumulator ==
 
== TYA - Transfer Y to Accumulator ==
 
{|
 
{|
Line 1,605: Line 1,962:
 
! N !! V !! T !! D !! I !! Z !! C
 
! N !! V !! T !! D !! I !! Z !! C
 
|-
 
|-
| ? || &nbsp; || 0 || &nbsp; || &nbsp; || ? || &nbsp;
+
| ? || || 0 || || || ? ||
 
|}
 
|}
 
<p>Copies the value in Y to the Accumulator.</p>
 
<p>Copies the value in Y to the Accumulator.</p>
{|
+
{| class="addressing"
 
|-
 
|-
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles
 
! Addressing Mode !! Syntax !! Opcode !! Bytes !! Cycles

Latest revision as of 19:08, 12 January 2019

Contents

ADC - Add with Carry

N V T D I Z C
 ?  ? 0  ?  ?

Add the value specified by the operand, and 1 if the Carry flag is set, to the value in the accumulator. If the result is too large to fit in the accumulator, the carry flag will be set, otherwise it will be cleared.

If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).

The overflow flag is not affected by this instruction if in Decimal mode; otherwise, if bit 7 of the result != bit 7 of the accumulator before the operation, and bit 7 of the accumulator before the operation == bit 7 of the value specified by the operand, the overflow flag is set, otherwise it is cleared. In other words, if we were to treat the accumulator and value specified by the operand as two's complement numbers, in the range of -128 to 127, the overflow flag will be set if the end result is outside of this range(otherwise it will be cleared).

If T=1 (the previous instruction is SET) the zero-page byte specified by the X register is used instead of the A register.

Here is a recap of the status register after use :

N Negative Flag Set if bit 7 is set
V Overflow Flag Set if bit 7 (sign bit for 2's complement number) is incorrect
T T Flag 0
D Decimal Flag N/A
I Interrupt Disable N/A
Z Zero Flag Set if A == 0
C Carry Flag Set if overflow in bit 7 occured


Addressing Mode Syntax Opcode Bytes Cycles
Immediate ADC #$ii $69 2 2
Zero Page ADC $zz $65 2 4
Zero Page, X ADC $zz,X $75 2 4
Absolute ADC $aaaa $6d 3 5
Absolute, X ADC $aaaa,X $7d 3 5
Absolute, Y ADC $aaaa,Y $79 3 5
Indirect ADC ($zzzz) $72 3 7
Indexed Indirect ADC ($zz,X) $61 2 7
Indirect, Index ADC ($zz),Y $71 2 7

AND - AND Accumulator with Memory

N V T D I Z C
 ? 0  ?

Performs a bit by bit logical and on the accumulator with the value specified by the operand.

Here is a recap of the processor status flags after use :

N Negative Flag Set if bit 7 is set
V Overflow Flag N/A
T T Flag 0
D Decimal Flag N/A
I Interrupt Disable N/A
Z Zero Flag Set if A == 0
C Carry Flag N/A


Addressing Mode Syntax Opcode Bytes Cycles
Immediate AND #$ii $29 2 2
Zero Page AND $zz $25 2 4
Zero Page, X AND $zz,X $35 2 4
Absolute AND $aaaa $2d 3 5
Absolute, X AND $aaaa,X $3d 3 5
Absolute, Y AND $aaaa,Y $39 3 5
Indirect AND ($zzzz) $32 3 7
Indexed Indirect AND ($zz,X) $21 2 7
Indirect, Index AND ($zz),Y $31 2 7

ASL - Arithmetic Shift Left

N V T D I Z C
 ? 0  ?  ?

Shifts the value at the location specified by the operand left by one bit, shifting in 0 to bit 0, and writes the result back to that location. Bit 7 of the value before the shift is copied to the Carry flag.

N Negative Flag Set if bit 7 of the result is set
V Overflow Flag N/A
T T Flag 0
D Decimal Flag N/A
I Interrupt Disable N/A
Z Zero Flag Set if A == 0
C Carry Flag Set to previous value of bit 7


Addressing Mode Syntax Opcode Bytes Cycles
Accumulator ASL A $0a 1 2
Zero Page ASL $zz $06 2 6
Zero Page, X ASL $zz,X $16 2 6
Absolute ASL $aaaa $0e 3 7
Absolute, X ASL $aaaa,X $1e 3 7

BBRn - Branch on Bit Reset n

N V T D I Z C
0

If Bit 'n' of the value at the effective address specified by the second operand is clear, branch to the address calculated from the second operand. The second operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Zero Page, Relative BBR0 $zz, $rr $0f 3 6*
Zero Page, Relative BBR1 $zz, $rr $1f 3 6*
Zero Page, Relative BBR2 $zz, $rr $2f 3 6*
Zero Page, Relative BBR3 $zz, $rr $3f 3 6*
Zero Page, Relative BBR4 $zz, $rr $4f 3 6*
Zero Page, Relative BBR5 $zz, $rr $5f 3 6*
Zero Page, Relative BBR6 $zz, $rr $6f 3 6*
Zero Page, Relative BBR7 $zz, $rr $7f 3 6*
* Add 2 extra cycles if branch is taken.

BBSn - Branch on Bit Set n

N V T D I Z C
0

If Bit 'n' of the value at the effective address specified by the operand is set, branch to the address calculated from the second operand. The second operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Zero Page, Relative BBS0 $zz, $rr $8f 3 6*
Zero Page, Relative BBS1 $zz, $rr $9f 3 6*
Zero Page, Relative BBS2 $zz, $rr $af 3 6*
Zero Page, Relative BBS3 $zz, $rr $bf 3 6*
Zero Page, Relative BBS4 $zz, $rr $cf 3 6*
Zero Page, Relative BBS5 $zz, $rr $df 3 6*
Zero Page, Relative BBS6 $zz, $rr $ef 3 6*
Zero Page, Relative BBS7 $zz, $rr $ff 3 6*

* Add 2 extra cycles if branch is taken.

BCC - Branch on Carry Clear

N V T D I Z C
0

If the carry flag is clear, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Relative BCC $rr $90 2 2(4 if branch taken)

BCS - Branch on Carry Set

N V T D I Z C
0

If the carry flag is set, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Relative BCS $rr $b0 2 2(4 if branch taken)

BEQ - Branch on Equal(Zero Set)

N V T D I Z C
0

If the zero flag is set, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Relative BEQ $rr $f0 2 2(4 if branch taken)

BIT - Test Memory Bits with Accumulator

N V T D I Z C
 ?  ? 0  ?

Performs an AND between the accumulator and the specified operand without storing the result. Bit 7 and 6 of the memory operand are respectively saved in the negative (N) and overflow (V) flags.

N Negative Flag Bit 7 of M
V Overflow Flag Bit 6 of M
T T Flag 0
D Decimal Flag N/A
I Interrupt Disable N/A
Z Zero Flag Set if A & M == 0
C Carry Flag N/A


Addressing Mode Syntax Opcode Bytes Cycles
Immediate BIT #$ii $89 2 2
Zero Page BIT $zz $24 2 4
Zero Page, X BIT $zz,X $34 2 4
Absolute BIT $aaaa $2c 3 5
Absolute, X BIT $aaaa,X $3c 3 5

BMI - Branch on Minus(Negative Set)

N V T D I Z C
0

If the negative flag is set, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Relative BMI $rr $30 2 2(4 if branch taken)

BNE - Branch on Not Equal(Zero Clear)

N V T D I Z C
0

If the zero flag is clear, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Relative BNE $rr $d0 2 2(4 if branch taken)

BPL - Branch on Plus(Negative Clear)

N V T D I Z C
0

If the negative flag is clear, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Relative BPL $rr $10 2 2(4 if branch taken)

BRA - Branch

N V T D I Z C
0

Unconditionally branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Relative BRA $rr $80 2 4

BRK - Break

N V T D I Z C
0 0 1

Forces a software interrupt using IRQ2's vector. Contrary to IRQs, BRK will push the status flags register with bit 4('B' flag) set.

Addressing Mode Syntax Opcode Bytes Cycles
Implied BRK $00 1 8

BSR - Branch to Subroutine

N V T D I Z C
0

The program counter (last byte of the BSR instruction) is pushed to stack and the CPU branches to the specified relative address.

Addressing Mode Syntax Opcode Bytes Cycles
Relative BSR $rr $44 2 8

BVC - Branch on Overflow Clear

N V T D I Z C
0

If the overflow flag is clear, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Relative BVC $rr $50 2 2

BVS - Branch on Overflow Set

N V T D I Z C
0

If the overflow flag is set, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing Mode Syntax Opcode Bytes Cycles
Relative BVS $rr $70 2 2

CLA - Clear Accumulator

N V T D I Z C
0

Clears the accumulator(reset to 0).

Addressing Mode Syntax Opcode Bytes Cycles
Implied CLA $62 1 2

CLC - Clear Carry Flag

N V T D I Z C
0 0

Clears the carry flag.

Addressing Mode Syntax Opcode Bytes Cycles
Implied CLC $18 1 2

CLD - Clear Decimal Flag

N V T D I Z C
0 0

Clears the decimal flag, disabling decimal mode.

Addressing Mode Syntax Opcode Bytes Cycles
Implied CLD $d8 1 2

CLI - Clear Interrupt Flag

N V T D I Z C
0 0

Clears the interrupt flag, allowing IRQs to be processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).

Addressing Mode Syntax Opcode Bytes Cycles
Implied CLI $58 1 2

CLV - Clear Overflow Flag

N V T D I Z C
0 0

Clears the overflow flag (V).

Addressing Mode Syntax Opcode Bytes Cycles
Implied CLV $b8 1 2

CLX - Clear X

N V T D I Z C
0

Clears the X register.

Addressing Mode Syntax Opcode Bytes Cycles
Implied CLX $82 1 2

CLY - Clear Y

N V T D I Z C
0

Clears the Y register.

Addressing Mode Syntax Opcode Bytes Cycles
Implied CLY $c2 1 2

CMP - Compare Accumulator with Memory

N V T D I Z C
 ? 0  ?  ?

The content of the operand is subtracted from the accumulator and the status register is set accordingly. The result of the subtraction is not stored.

N Negative Flag Set if bit 7 of the result is set
V Overflow Flag N/A
T T Flag 0
D Decimal Flag N/A
I Interrupt Disable N/A
Z Zero Flag Set if A == M
C Carry Flag Set if A >= M


Addressing Mode Syntax Opcode Bytes Cycles
Immediate CMP #$ii $c9 2 2
Zero Page CMP $zz $c5 2 4
Zero Page, X CMP $zz,X $d5 2 4
Absolute CMP $aaaa $cd 3 5
Absolute, X CMP $aaaa,X $dd 3 5
Absolute, Y CMP $aaaa,Y $d9 3 5
Indirect CMP ($zzzz) $d2 3 7
Indexed Indirect CMP ($zz,X) $c1 2 7
Indirect, Index CMP ($zz),Y $d1 2 7

CPX - Compare X with Memory

N V T D I Z C
 ? 0  ?  ?

The content of the operand is subtracted from the X register and the status register is set accordingly. The result of the subtraction is not stored.

N Negative Flag Set if bit 7 of the result is set
V Overflow Flag N/A
T T Flag 0
D Decimal Flag N/A
I Interrupt Disable N/A
Z Zero Flag Set if X == M
C Carry Flag Set if X >= M


Addressing Mode Syntax Opcode Bytes Cycles
Immediate CPX #$ii $e0 2 2
Zero Page CPX $zz $e4 2 4
Absolute CPX $aaaa $ec 3 5

CPY - Compare Y with Memory

N V T D I Z C
 ? 0  ?  ?

The content of the operand is subtracted from the Y register and the status register is set accordingly. The result of the subtraction is not stored.

N Negative Flag Set if bit 7 of the result is set
V Overflow Flag N/A
T T Flag 0
D Decimal Flag N/A
I Interrupt Disable N/A
Z Zero Flag Set if Y == M
C Carry Flag Set if Y >= M


Addressing Mode Syntax Opcode Bytes Cycles
Immediate CPY #$ii $c0 2 2
Zero Page CPY $zz $c4 2 4
Absolute CPY $aaaa $cc 3 5

CSH - Change Speed High

N V T D I Z C
0

Set CPU to high speed mode (7.16 MHz).

Addressing Mode Syntax Opcode Bytes Cycles
Implied CSH $d4 1 3

CSL - Change Speed Low

N V T D I Z C
0

Set CPU to low speed mode (1.78 MHz).

Addressing Mode Syntax Opcode Bytes Cycles
Implied CSL $54 1 3

DEC - Decrement

N V T D I Z C
 ? 0  ?

Decrement the operand by 1.

N Negative Flag Set if bit 7 of the result is set
V Overflow Flag N/A
T T Flag 0
D Decimal Flag N/A
I Interrupt Disable N/A
Z Zero Flag Set if the result is zero
C Carry Flag N/A


Addressing Mode Syntax Opcode Bytes Cycles
Zero Page DEC $zz $c6 2 6
Zero Page, X DEC $zz,X $d6 2 6
Absolute DEC $aaaa $ce 3 7
Absolute, X DEC $aaaa,X $de 3 7

DEX - Decrement X

N V T D I Z C
 ? 0  ?

Decrement the X register by 1.

N Negative Flag Set if bit 7 of the X register is set
V Overflow Flag N/A
T T Flag 0
D Decimal Flag N/A
I Interrupt Disable N/A
Z Zero Flag Set if the X register is zero
C Carry Flag N/A


Addressing Mode Syntax Opcode Bytes Cycles
Implied DEX $ca 1 2

DEY - Decrement Y

N V T D I Z C
 ? 0  ?

Decrement the Y register by 1.

N Negative Flag Set if bit 7 of the Y register is set
V Overflow Flag N/A
T T Flag 0
D Decimal Flag N/A
I Interrupt Disable N/A
Z Zero Flag Set if the Y register is zero
C Carry Flag N/A


Addressing Mode Syntax Opcode Bytes Cycles
Implied DEY $88 1 2

EOR - Exclusive OR Accumulator with Memory

N V T D I Z C
 ? 0  ?

Logically XOR the value referenced by the operand to the accumulator.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate EOR #$ii $49 2 2
Zero Page EOR $zz $45 2 4
Zero Page, X EOR $zz,X $55 2 4
Absolute EOR $aaaa $4d 3 5
Absolute, X EOR $aaaa,X $5d 3 5
Absolute, Y EOR $aaaa,Y $59 3 5
Indirect EOR ($zzzz) $52 3 7
Indexed Indirect EOR ($zz,X) $41 2 7
Indirect, Index EOR ($zz),Y $51 2 7

INC - Increment

N V T D I Z C
 ? 0  ?

Increments the value of the location specified by the operand by one. The Carry flag is not used, nor is it modified.

Addressing Mode Syntax Opcode Bytes Cycles
Accumulator INC A $1a 1 2
Zero Page INC $zz $e6 2 6
Zero Page, X INC $zz,X $f6 2 6
Absolute INC $aaaa $ee 3 7
Absolute, X INC $aaaa,X $fe 3 7

INX - Increment X

N V T D I Z C
 ? 0  ?

Increments the value in the X register by one. The Carry flag is not used, nor is it modified.

Addressing Mode Syntax Opcode Bytes Cycles
Implied INX $e8 1 2

INY - Increment Y

N V T D I Z C
 ? 0  ?

Increments the value in the Y register by one. The Carry flag is not used, nor is it modified.

Addressing Mode Syntax Opcode Bytes Cycles
Implied INY $c8 1 2

JMP - Jump

N V T D I Z C
0

Transfers control(sets the program counter) to the effective address calculated from the operand.

Addressing Mode Syntax Opcode Bytes Cycles
Absolute JMP $aaaa $4c 3 4
Indirect JMP ($zzzz) $6c 3 7
Indexed Indirect JMP ($zzzz,X) $7c 3 7

JSR - Jump to Subroutine

N V T D I Z C
0

Push the current program counter value (minus 1) onto the stack and set it to the address specified in the second operand.

Addressing Mode Syntax Opcode Bytes Cycles
Absolute JSR $aaaa $20 3 7

LDA - Load Accumulator

N V T D I Z C
 ? 0  ?

Loads the accumulator with the value at the effective address.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate LDA #$ii $a9 2 2
Zero Page LDA $zz $a5 2 4
Zero Page, X LDA $zz,X $b5 2 4
Absolute LDA $aaaa $ad 3 5
Absolute, X LDA $aaaa,X $bd 3 5
Absolute, Y LDA $aaaa,Y $b9 3 5
Indirect LDA ($zzzz) $b2 3 7
Indexed Indirect LDA ($zz,X) $a1 2 7
Indirect, Index LDA ($zz),Y $b1 2 7

LDX - Load X

N V T D I Z C
 ? 0  ?

Loads the X register with the value at the effective address.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate LDX #$ii $a2 2 2
Zero Page LDX $zz $a6 2 4
Zero Page, Y LDX $zz,Y $b6 2 4
Absolute LDX $aaaa $ae 3 5
Absolute, Y LDX $aaaa,Y $be 3 5

LDY - Load Y

N V T D I Z C
 ? 0  ?

Loads the Y register with the value at the effective address.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate LDY #$ii $a0 2 2
Zero Page LDY $zz $a4 2 4
Zero Page, X LDY $zz,X $b4 2 4
Absolute LDY $aaaa $ac 3 5
Absolute, X LDY $aaaa,X $bc 3 5

LSR - Logical Shift Right

N V T D I Z C
 ? 0  ? 0
Addressing Mode Syntax Opcode Bytes Cycles
Accumulator LSR A $4a 1 2
Zero Page LSR $zz $46 2 6
Zero Page, X LSR $zz,X $56 2 6
Absolute LSR $aaaa $4e 3 7
Absolute, X LSR $aaaa,X $5e 3 7

NOP - No Operation

N V T D I Z C
0
Addressing Mode Syntax Opcode Bytes Cycles
Implied NOP $ea 1 2

ORA - OR Accumulator with Memory

N V T D I Z C
 ? 0  ?

Logically OR the value referenced by the operand with the accumulator, storing the result in the accumulator.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate ORA #$ii $09 2 2
Zero Page ORA $zz $05 2 4
Zero Page, X ORA $zz,X $15 2 4
Absolute ORA $aaaa $0d 3 5
Absolute, X ORA $aaaa,X $1d 3 5
Absolute, Y ORA $aaaa,Y $19 3 5
Indirect ORA ($zzzz) $12 3 7
Indexed Indirect ORA ($zz,X) $01 2 7
Indirect, Index ORA ($zz),Y $11 2 7

PHA - Push A

N V T D I Z C
0

Pushes the accumulator to the stack.

Addressing Mode Syntax Opcode Bytes Cycles
Implied PHA $48 1 3

PHP - Push P

N V T D I Z C
0

Pushes the status flags(1 byte) to the stack.

Addressing Mode Syntax Opcode Bytes Cycles
Implied PHP $08 1 3

PHX - Push X

N V T D I Z C
0

Pushes the X register to the stack.

Addressing Mode Syntax Opcode Bytes Cycles
Implied PHX $da 1 3

PHY - Push Y

N V T D I Z C
0

Pushes the Y register to the stack.

Addressing Mode Syntax Opcode Bytes Cycles
Implied PHY $5a 1 3

PLA - Pull A

N V T D I Z C
 ? 0  ?

Pulls a value off the stack, and stores the value in the accumulator.

Addressing Mode Syntax Opcode Bytes Cycles
Implied PLA $68 1 4

PLP - Pull P

N V T D I Z C
 ?  ?  ?  ?  ?  ?  ?
Addressing Mode Syntax Opcode Bytes Cycles
Implied PLP $28 1 4

PLX - Pull X

N V T D I Z C
 ? 0  ?

Pulls a value off the stack, and stores the value in the X register.

Addressing Mode Syntax Opcode Bytes Cycles
Implied PLX $fa 1 4

PLY - Pull Y

N V T D I Z C
 ? 0  ?

Pulls a value off the stack, and stores the value in Y register.

Addressing Mode Syntax Opcode Bytes Cycles
Implied PLY $7a 1 4

RMBn - Reset Memory Bit n

N V T D I Z C
0

Reads the zero-page address specified by the operand, resets(clears) the bit "n", and then writes it back to the aforementioned address.

Addressing Mode Syntax Opcode Bytes Cycles
Zero Page RMB0 $zz $07 2 7
Zero Page RMB1 $zz $17 2 7
Zero Page RMB2 $zz $27 2 7
Zero Page RMB3 $zz $37 2 7
Zero Page RMB4 $zz $47 2 7
Zero Page RMB5 $zz $57 2 7
Zero Page RMB6 $zz $67 2 7
Zero Page RMB7 $zz $77 2 7

ROL - Rotate Left

N V T D I Z C
 ? 0  ?  ?
Addressing Mode Syntax Opcode Bytes Cycles
Accumulator ROL A $2a 1 2
Zero Page ROL $zz $26 2 6
Zero Page, X ROL $zz,X $36 2 6
Absolute ROL $aaaa $2e 3 7
Absolute, X ROL $aaaa,X $3e 3 7

ROR - Rotate Right

N V T D I Z C
 ? 0  ?  ?
Addressing Mode Syntax Opcode Bytes Cycles
Accumulator ROR A $6a 1 2
Zero Page ROR $zz $66 2 6
Zero Page, X ROR $zz,X $76 2 6
Absolute ROR $aaaa $6e 3 7
Absolute, X ROR $aaaa,X $7e 3 7

RTI - Return from Interrupt

N V T D I Z C
 ?  ?  ?  ?  ?  ?  ?
Addressing Mode Syntax Opcode Bytes Cycles
Implied RTI $40 1 7

RTS - Return from Subroutine

N V T D I Z C
0
Addressing Mode Syntax Opcode Bytes Cycles
Implied RTS $60 1 7

SAX - Swap A and X

N V T D I Z C
0

Swaps the values in the accumulator and X register.

Addressing Mode Syntax Opcode Bytes Cycles
Implied SAX $22 1 3

SAY - Swap A and Y

N V T D I Z C
0

Swap the values in the accumulator and Y register.

Addressing Mode Syntax Opcode Bytes Cycles
Implied SAY $42 1 3

SBC - Subtract with Borrow

N V T D I Z C
 ?  ? 0  ?  ?

If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).

The overflow flag is not affected by this instruction if in Decimal mode.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate SBC #$ii $e9 2 2
Zero Page SBC $zz $e5 2 4
Zero Page, X SBC $zz,X $f5 2 4
Absolute SBC $aaaa $ed 3 5
Absolute, X SBC $aaaa,X $fd 3 5
Absolute, Y SBC $aaaa,Y $f9 3 5
Indirect SBC ($zzzz) $f2 3 7
Indexed Indirect SBC ($zz,X) $e1 2 7
Indirect, Index SBC ($zz),Y $f1 2 7

SEC - Set Carry Flag

N V T D I Z C
0 1

Sets the carry flag.

Addressing Mode Syntax Opcode Bytes Cycles
Implied SEC $38 1 2

SED - Set Decimal Flag

N V T D I Z C
0 1

Sets the decimal flag, enabling decimal mode.

Addressing Mode Syntax Opcode Bytes Cycles
Implied SED $f8 1 2

SEI - Set Interrupt Flag

N V T D I Z C
0 1

Sets the interrupt flag, preventing IRQs from being processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).

Addressing Mode Syntax Opcode Bytes Cycles
Implied SEI $78 1 2

SET - Set T Flag

N V T D I Z C
1

Sets the T flag, which changes the behavior of the next instruction if the next instruction is ADC, AND, EOR, ORA, or SBC, in which case the operation is performed on the zero-page address specified by the X register, instead of the accumulator.

Note that interrupt processing preserves the T-flag, and clears the T-flag in the interrupt handler, so a programmer needn't worry about an interrupt occuring between SET and the next instruction.

Addressing Mode Syntax Opcode Bytes Cycles
Implied SET $f4 1 2

SMBn - Set Memory Bit n

N V T D I Z C
0

Reads the zero-page address specified by the operand, sets the bit "n", and then writes it back to the aforementioned address.

Addressing Mode Syntax Opcode Bytes Cycles
Zero Page SMB0 $zz $87 2 7
Zero Page SMB1 $zz $97 2 7
Zero Page SMB2 $zz $a7 2 7
Zero Page SMB3 $zz $b7 2 7
Zero Page SMB4 $zz $c7 2 7
Zero Page SMB5 $zz $d7 2 7
Zero Page SMB6 $zz $e7 2 7
Zero Page SMB7 $zz $f7 2 7

ST0 - Store (HuC6270) VDC No. 0

N V T D I Z C
0

Writes the immediate value to the physical address $1FE000, the (HuC6270) VDC's address register.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate ST0 #$ii $03 2 5

ST1 - Store (HuC6270) VDC No. 1

N V T D I Z C
0

Writes the immediate value to the physical address $1FE002, the (HuC6270) VDC's lower data register.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate ST1 #$ii $13 2 5

ST2 - Store (HuC6270) VDC No. 2

N V T D I Z C
0

Writes the immediate value to the physical address $1FE003, the (HuC6270) VDC's upper data register.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate ST2 #$ii $23 2 5

STA - Store Accumulator

N V T D I Z C
0

Stores the value in the accumulator to the effective address specified by the operand.

Addressing Mode Syntax Opcode Bytes Cycles
Zero Page STA $zz $85 2 4
Zero Page, X STA $zz,X $95 2 4
Absolute STA $aaaa $8d 3 5
Absolute, X STA $aaaa,X $9d 3 5
Absolute, Y STA $aaaa,Y $99 3 5
Indirect STA ($zzzz) $92 3 7
Indexed Indirect STA ($zz,X) $81 2 7
Indirect, Index STA ($zz),Y $91 2 7

STX - Store X

N V T D I Z C
0

Stores the value in the X register to the effective address specified by the operand.

Addressing Mode Syntax Opcode Bytes Cycles
Zero Page STX $zz $86 2 4
Zero Page, Y STX $zz,Y $96 2 4
Absolute STX $aaaa $8e 3 5

STY - Store Y

N V T D I Z C
0

Stores the value in the Y register to the effective address specified by the operand.

Addressing Mode Syntax Opcode Bytes Cycles
Zero Page STY $zz $84 2 4
Zero Page, X STY $zz,X $94 2 4
Absolute STY $aaaa $8c 3 5

STZ - Store Zero

N V T D I Z C
0

Stores zero to the effective address specified by the operand.

Addressing Mode Syntax Opcode Bytes Cycles
Zero Page STZ $zz $64 2 4
Zero Page, X STZ $zz,X $74 2 4
Absolute STZ $aaaa $9c 3 5
Absolute, X STZ $aaaa,X $9e 3 5

SXY - Swap X and Y

N V T D I Z C
0

Swaps the values in the X register and the Y register.

Addressing Mode Syntax Opcode Bytes Cycles
Implied SXY $02 1 3

TAI - Transfer Alternate Increment

N V T D I Z C
0

Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):

Alternate = 0
Do
 Value = Read(ssss + Alternate)
 Write(dddd, value)
 dddd = dddd + 1
 llll = llll - 1
 Alternate = Alternate ^ 1
While llll != 0

It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0" will be effectively treated as a length of "65536".

Please note that the cycles-per-byte-transferred will be higher if (HuC6270) VDC registers are used as source and/or destination.

All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.

Addressing Mode Syntax Opcode Bytes Cycles
Block Transfer TAI $ssss, $dddd, $llll $f3 7 17 + 6 * llll

TAM - Transfer Accumulator to MPRs

N V T D I Z C
0

Copies the value in the accumulator to each MPR with the corresponding bit set in the immediate operand, eg. TAM #$41 will load MPR0 and MPR6 with the value in the accumulator. If no bits are set, no transfer will occur, and the instruction is effectively a 5-cycle NOP.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate TAM #$ii $53 2 5

TAX - Transfer Accumulator to X

N V T D I Z C
 ? 0  ?

Copies the value of the accumulator to the X register.

Addressing Mode Syntax Opcode Bytes Cycles
Implied TAX $aa 1 2

TAY - Transfer Accumulator to Y

N V T D I Z C
 ? 0  ?

Copies the value of the accumulator to the Y register.

Addressing Mode Syntax Opcode Bytes Cycles
Implied TAY $a8 1 2

TDD - Transfer Decrement Decrement

N V T D I Z C
0

Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):

Do
 Value = Read(ssss)
 Write(dddd, value)
 ssss = ssss - 1
 dddd = dddd - 1
 llll = llll - 1
While llll != 0

It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0" will be effectively treated as a length of "65536".

Please note that the cycles-per-byte-transferred will be higher if (HuC6270) VDC registers are used as source and/or destination.

All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.

Addressing Mode Syntax Opcode Bytes Cycles
Block Transfer TDD $ssss, $dddd, $llll $c3 7 17 + 6 * llll

TIA - Transfer Increment Alternate

N V T D I Z C
0


Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):

Alternate = 0
Do
 Value = Read(ssss)
 Write(dddd + Alternate, Value)
 ssss = ssss + 1
 llll = llll - 1
 Alternate = Alternate ^ 1
While llll != 0

It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0" will be effectively treated as a length of "65536".

All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.

Please note that the cycles-per-byte-transferred will be higher if (HuC6270) VDC registers are used as source and/or destination.

Addressing Mode Syntax Opcode Bytes Cycles
Block Transfer TIA $ssss, $dddd, $llll $e3 7 17 + 6 * llll

TII - Transfer Increment Increment

N V T D I Z C
0

Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):

Do
 Value = Read(ssss)
 Write(dddd, Value)
 ssss = ssss + 1
 dddd = dddd + 1
 llll = llll - 1
While llll != 0

It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0" will be effectively treated as a length of "65536".

All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.

Please note that the cycles-per-byte-transferred will be higher if (HuC6270) VDC registers are used as source and/or destination.

Addressing Mode Syntax Opcode Bytes Cycles
Block Transfer TII $ssss, $dddd, $llll $73 7 17 + 6 * llll

TIN - Transfer Increment

N V T D I Z C
0

Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):

Do
 Value = Read(ssss)
 Write(dddd, value)
 ssss = ssss + 1
 llll = llll - 1
While llll != 0

It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0" will be effectively treated as a length of "65536".

All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.

Please note that the cycles-per-byte-transferred will be higher if (HuC6270) VDC registers are used as source and/or destination.

Addressing Mode Syntax Opcode Bytes Cycles
Block Transfer TIN $ssss, $dddd, $llll $d3 7 17 + 6 * llll

TMA - Transfer MPR to Accumulator

N V T D I Z C
0

Copies the value in the MPR, specified by the corresponding bit being set in the immediate operand, to the accumulator. If an immediate value of $00 is used, the accumulator will be loaded with the last value transfered by TAM(note that if an immediate value of $00 is used with TAM, no transfer occurs, and as such won't be read back if an immediate value of $00 is used with TMA). Undefined behavior results if multiple bits are set.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate TMA #$ii $43 2 4

TRB - Test and Reset Bits against Accumulator

N V T D I Z C
 ?  ? 0  ?

Loads the value specified by the effective address of the operand, clears all bits whose corresponding bits are set in the accumulator(result = value & ~accumulator), and stores the result to the aforementioned address.

The zero flag is set according to the result. The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address, before it is operated on.

Addressing Mode Syntax Opcode Bytes Cycles
Zero Page TRB $zz $14 2 6
Absolute TRB $aaaa $1c 3 7

TSB - Test and Set Bits against Accumulator

N V T D I Z C
 ?  ? 0  ?

Loads the value specified by the effective address of the operand, sets all bits whose corresponding bits are set in the accumulator(result = value & ~accumulator), and stores the result to the aforementioned address.

The zero flag is set according to the result. The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address, before it is operated on.

Addressing Mode Syntax Opcode Bytes Cycles
Zero Page TSB $zz $04 2 6
Absolute TSB $aaaa $0c 3 7

TST - Test

N V T D I Z C
 ?  ? 0  ?

The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address(they are *not* set as the result of the AND operation used to determine the Z flag's state).

The Z flag is determined according to the result of logically AND'ing the immediate value and the value at the effective address.

Addressing Mode Syntax Opcode Bytes Cycles
Immediate, Zero Page TST #$ii, $zz $83 3 7
Immediate, Zero Page, X TST #$ii, $zz, X $a3 3 7
Immediate, Absolute TST #$ii, $aaaa $93 4 8
Immediate, Absolute, X TST #$ii, $aaaa, X $b3 4 8

TSX - Transfer Stack Pointer to X

N V T D I Z C
 ? 0  ?
Addressing Mode Syntax Opcode Bytes Cycles
Implied TSX $ba 1 2

TXA - Transfer X to A

N V T D I Z C
 ? 0  ?

Copies the value in the X register to the Accumulator.

Addressing Mode Syntax Opcode Bytes Cycles
Implied TXA $8a 1 2

TXS - Track X to Stack Pointer

N V T D I Z C
0

Copies the value in X to the stack pointer.

Addressing Mode Syntax Opcode Bytes Cycles
Implied TXS $9a 1 2

TYA - Transfer Y to Accumulator

N V T D I Z C
 ? 0  ?

Copies the value in Y to the Accumulator.

Addressing Mode Syntax Opcode Bytes Cycles
Implied TYA $98 1 2