Difference between revisions of "HuC6280 Instruction Set"

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== ADC - Add with Carry ==
 
== ADC - Add with Carry ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>?</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>?</td></tr></table>
 
+
<p>Add the value specified by the operand, and 1 if the Carry flag is set, to the value in the accumulator.  If the result is too large to fit in the accumulator, the carry flag will be set, otherwise it will be cleared.</p>
<tr style="background: #efefef">
+
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).</p>
<td><b>N</b>
+
<p>The overflow flag is not affected by this instruction if in Decimal mode; otherwise, if bit7 of the result&nbsp;!= bit7 of the accumulator before the operation, and bit7 of the accumulator before the operation == bit7 of the value specified by the operand, the overflow flag is set, otherwise it is cleared.  In other words, if we were to treat the accumulator and value specified by the operand as <a href="http://en.wikipedia.org/wiki/Two%27s_complement" class='external text' title="http://en.wikipedia.org/wiki/Two%27s_complement" rel="nofollow">two's complement</a> numbers, in the range of -128 to 127, the overflow flag will be set if the end result is outside of this range(otherwise it will be cleared).</p>
</td><td><b>V</b>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>ADC #$ii</td><td>$69</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>ADC $zz</td><td>$65</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>ADC $zz,X</td><td>$75</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>ADC $aaaa</td><td>$6d</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>ADC $aaaa,X</td><td>$7d</td><td>3</td><td>5</td></tr><tr><td>Absolute, Y</td><td>ADC $aaaa,Y</td><td>$79</td><td>3</td><td>5</td></tr><tr><td>Indirect</td><td>ADC ($zz)</td><td>$72</td><td>3</td><td>7</td></tr><tr><td>Indexed Indirect</td><td>ADC ($zz,X)</td><td>$61</td><td>2</td><td>7</td></tr><tr><td>Indirect, Index</td><td>ADC ($zz),Y</td><td>$71</td><td>2</td><td>7</td></tr></table>
</td><td><b>T</b>
+
</td><td><b>D</b>
+
 
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>?
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>?
+
</td></tr></table>
+
<p>Add the value specified by the operand, and 1 if the Carry flag is set, to the value in the accumulator.  If the result is too large to fit in the accumulator, the carry flag will be set, otherwise it will be cleared.
+
 
+
</p><p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).
+
</p><p>The overflow flag is not affected by this instruction if in Decimal mode; otherwise, if bit7 of the result&nbsp;!= bit7 of the accumulator before the operation, and bit7 of the accumulator before the operation == bit7 of the value specified by the operand, the overflow flag is set, otherwise it is cleared.  In other words, if we were to treat the accumulator and value specified by the operand as <a href="http://en.wikipedia.org/wiki/Two%27s_complement" class='external text' title="http://en.wikipedia.org/wiki/Two%27s_complement" rel="nofollow">two's complement</a> numbers, in the range of -128 to 127, the overflow flag will be set if the end result is outside of this range(otherwise it will be cleared).
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
 
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>ADC #$ii
+
</td><td>$69
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>ADC $zz
+
</td><td>$65
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
 
+
<tr>
+
<td>Zero Page, X
+
</td><td>ADC $zz,X
+
</td><td>$75
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>ADC $aaaa
+
</td><td>$6d
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>ADC $aaaa,X
+
 
+
</td><td>$7d
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>ADC $aaaa,Y
+
</td><td>$79
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Indirect
+
</td><td>ADC ($zz)
+
</td><td>$72
+
</td><td>3
+
</td><td>7
+
 
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
</td><td>ADC ($zz,X)
+
</td><td>$61
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indirect, Index
+
</td><td>ADC ($zz),Y
+
</td><td>$71
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== AND - AND Accumulator with Memory ==
 
== AND - AND Accumulator with Memory ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>AND #$ii</td><td>$29</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>AND $zz</td><td>$25</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>AND $zz,X</td><td>$35</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>AND $aaaa</td><td>$2d</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>AND $aaaa,X</td><td>$3d</td><td>3</td><td>5</td></tr><tr><td>Absolute, Y</td><td>AND $aaaa,Y</td><td>$39</td><td>3</td><td>5</td></tr><tr><td>Indirect</td><td>AND ($zz)</td><td>$32</td><td>3</td><td>7</td></tr><tr><td>Indexed Indirect</td><td>AND ($zz,X)</td><td>$21</td><td>2</td><td>7</td></tr><tr><td>Indirect, Index</td><td>AND ($zz),Y</td><td>$31</td><td>2</td><td>7</td></tr></table>
 
+
<p><br /></p>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>AND #$ii
+
</td><td>$29
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>AND $zz
+
 
+
</td><td>$25
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>AND $zz,X
+
</td><td>$35
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>AND $aaaa
+
</td><td>$2d
+
</td><td>3
+
</td><td>5
+
 
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>AND $aaaa,X
+
</td><td>$3d
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>AND $aaaa,Y
+
</td><td>$39
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Indirect
+
 
+
</td><td>AND ($zz)
+
</td><td>$32
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
</td><td>AND ($zz,X)
+
</td><td>$21
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indirect, Index
+
</td><td>AND ($zz),Y
+
</td><td>$31
+
</td><td>2
+
 
+
</td><td>7
+
</td></tr>
+
</table>
+
<p><br />
+
</p>
+
 
== ASL - Arithmetic Shift Left ==
 
== ASL - Arithmetic Shift Left ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>?</td></tr></table>
 
+
<p>Shifts the value at the location specified by the operand left by one bit, shifting in 0 to Bit0, and writes the result back to that location.  Bit7 of the value before the shift is copied to the Carry flag.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Accumulator</td><td>ASL A</td><td>$0a</td><td>1</td><td>2</td></tr><tr><td>Zero Page</td><td>ASL $zz</td><td>$06</td><td>2</td><td>6</td></tr><tr><td>Zero Page, X</td><td>ASL $zz,X</td><td>$16</td><td>2</td><td>6</td></tr><tr><td>Absolute</td><td>ASL $aaaa</td><td>$0e</td><td>3</td><td>7</td></tr><tr><td>Absolute, X</td><td>ASL $aaaa,X</td><td>$1e</td><td>3</td><td>7</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>?
+
 
+
</td></tr></table>
+
<p>Shifts the value at the location specified by the operand left by one bit, shifting in 0 to Bit0, and writes the result back to that location.  Bit7 of the value before the shift is copied to the Carry flag.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
 
+
<tr>
+
<td>Accumulator
+
</td><td>ASL A
+
</td><td>$0a
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>ASL $zz
+
</td><td>$06
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>ASL $zz,X
+
 
+
</td><td>$16
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>ASL $aaaa
+
</td><td>$0e
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>ASL $aaaa,X
+
</td><td>$1e
+
</td><td>3
+
</td><td>7
+
 
+
</td></tr>
+
</table>
+
 
== BBRn - Branch on Bit Reset n ==
 
== BBRn - Branch on Bit Reset n ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If Bit 'n' of the value at the effective address specified by the second operand is clear, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If Bit 'n' of the value at the effective address specified by the second operand is clear, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Zero Page, Relative</td><td>BBR0 $zz, $rrrr</td><td>$0f</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBR1 $zz, $rrrr</td><td>$1f</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBR2 $zz, $rrrr</td><td>$2f</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBR3 $zz, $rrrr</td><td>$3f</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBR4 $zz, $rrrr</td><td>$4f</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBR5 $zz, $rrrr</td><td>$5f</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBR6 $zz, $rrrr</td><td>$6f</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBR7 $zz, $rrrr</td><td>$7f</td><td>3</td><td>6*</td></tr></table>
 
+
<pre>* Add 2 extra cycles if branch is taken.</pre>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBR0 $zz, $rrrr
+
 
+
</td><td>$0f
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBR1 $zz, $rrrr
+
</td><td>$1f
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBR2 $zz, $rrrr
+
</td><td>$2f
+
</td><td>3
+
</td><td>6*
+
 
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBR3 $zz, $rrrr
+
</td><td>$3f
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBR4 $zz, $rrrr
+
</td><td>$4f
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
 
+
</td><td>BBR5 $zz, $rrrr
+
</td><td>$5f
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBR6 $zz, $rrrr
+
</td><td>$6f
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBR7 $zz, $rrrr
+
</td><td>$7f
+
</td><td>3
+
 
+
</td><td>6*
+
</td></tr>
+
</table>
+
<pre>* Add 2 extra cycles if branch is taken.
+
</pre>
+
 
== BBSn - Branch on Bit Set n ==
 
== BBSn - Branch on Bit Set n ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
 
+
</td></tr></table>
+
 
<p>If Bit 'n' of the value at the effective address specified by the operand is set, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If Bit 'n' of the value at the effective address specified by the operand is set, branch to the address calculated from the second operand.  The second operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Zero Page, Relative</td><td>BBS0 $zz, $rrrr</td><td>$8f</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBS1 $zz, $rrrr</td><td>$9f</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBS2 $zz, $rrrr</td><td>$af</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBS3 $zz, $rrrr</td><td>$bf</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBS4 $zz, $rrrr</td><td>$cf</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBS5 $zz, $rrrr</td><td>$df</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBS6 $zz, $rrrr</td><td>$ef</td><td>3</td><td>6*</td></tr><tr><td>Zero Page, Relative</td><td>BBS7 $zz, $rrrr</td><td>$ff</td><td>3</td><td>6*</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<pre>* Add 2 extra cycles if branch is taken.</pre>
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
 
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBS0 $zz, $rrrr
+
</td><td>$8f
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBS1 $zz, $rrrr
+
</td><td>$9f
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
 
+
</td><td>BBS2 $zz, $rrrr
+
</td><td>$af
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBS3 $zz, $rrrr
+
</td><td>$bf
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBS4 $zz, $rrrr
+
</td><td>$cf
+
</td><td>3
+
 
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBS5 $zz, $rrrr
+
</td><td>$df
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
<td>Zero Page, Relative
+
</td><td>BBS6 $zz, $rrrr
+
</td><td>$ef
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
<tr>
+
 
+
<td>Zero Page, Relative
+
</td><td>BBS7 $zz, $rrrr
+
</td><td>$ff
+
</td><td>3
+
</td><td>6*
+
</td></tr>
+
</table>
+
<pre>* Add 2 extra cycles if branch is taken.
+
</pre>
+
 
== BCC - Branch on Carry Clear ==
 
== BCC - Branch on Carry Clear ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
 
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
 
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the carry flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the carry flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Relative</td><td>BCC $rrrr</td><td>$90</td><td>2</td><td>2(4 if branch taken)</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BCC $rrrr
+
</td><td>$90
+
</td><td>2
+
</td><td>2(4 if branch taken)
+
</td></tr>
+
</table>
+
 
== BCS - Branch on Carry Set ==
 
== BCS - Branch on Carry Set ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the carry flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the carry flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
<p><br /></p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Relative</td><td>BCS $rrrr</td><td>$b0</td><td>2</td><td>2(4 if branch taken)</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BCS $rrrr
+
</td><td>$b0
+
</td><td>2
+
</td><td>2(4 if branch taken)
+
</td></tr>
+
</table>
+
 
+
 
== BEQ - Branch on Equal(Zero Set) ==
 
== BEQ - Branch on Equal(Zero Set) ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the zero flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the zero flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
<p><br /></p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Relative</td><td>BEQ $rrrr</td><td>$f0</td><td>2</td><td>2(4 if branch taken)</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BEQ $rrrr
+
</td><td>$f0
+
 
+
</td><td>2
+
</td><td>2(4 if branch taken)
+
</td></tr>
+
</table>
+
 
== BIT - Test Memory Bits with Accumulator ==
 
== BIT - Test Memory Bits with Accumulator ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>?</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>BIT #$ii</td><td>$89</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>BIT $zz</td><td>$24</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>BIT $zz,X</td><td>$34</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>BIT $aaaa</td><td>$2c</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>BIT $aaaa,X</td><td>$3c</td><td>3</td><td>5</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
 
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>?
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>BIT #$ii
+
</td><td>$89
+
 
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>BIT $zz
+
</td><td>$24
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>BIT $zz,X
+
</td><td>$34
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
 
+
<tr>
+
<td>Absolute
+
</td><td>BIT $aaaa
+
</td><td>$2c
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>BIT $aaaa,X
+
</td><td>$3c
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
</table>
+
 
== BMI - Branch on Minus(Negative Set) ==
 
== BMI - Branch on Minus(Negative Set) ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the negative flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the negative flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
<p><br /></p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Relative</td><td>BMI $rrrr</td><td>$30</td><td>2</td><td>2(4 if branch taken)</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
 
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BMI $rrrr
+
</td><td>$30
+
</td><td>2
+
</td><td>2(4 if branch taken)
+
 
+
</td></tr>
+
</table>
+
 
== BNE - Branch on Not Equal(Zero Clear) ==
 
== BNE - Branch on Not Equal(Zero Clear) ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the zero flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the zero flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
<p><br /></p>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Relative</td><td>BNE $rrrr</td><td>$d0</td><td>2</td><td>2(4 if branch taken)</td></tr></table>
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
 
+
</td><td>BNE $rrrr
+
</td><td>$d0
+
</td><td>2
+
</td><td>2(4 if branch taken)
+
</td></tr>
+
</table>
+
 
== BPL - Branch on Plus(Negative Clear) ==
 
== BPL - Branch on Plus(Negative Clear) ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
 
+
</td></tr></table>
+
 
<p>If the negative flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the negative flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
<p><br /></p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Relative</td><td>BPL $rrrr</td><td>$10</td><td>2</td><td>2(4 if branch taken)</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
 
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BPL $rrrr
+
</td><td>$10
+
</td><td>2
+
</td><td>2(4 if branch taken)
+
</td></tr>
+
</table>
+
 
== BRA - Branch ==
 
== BRA - Branch ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
 
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
 
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>Unconditionally branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>Unconditionally branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p><br />
+
<p><br /></p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Relative</td><td>BRA $rrrr</td><td>$80</td><td>2</td><td>4</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BRA $rrrr
+
</td><td>$80
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
</table>
+
 
== BRK - Break ==
 
== BRK - Break ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>0</td><td>1</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Forces a software interrupt using <a href="/index.php?title=IRQ2&amp;action=edit" class="new" title="IRQ2">IRQ2</a>'s vector.  Contrary to IRQs, BRK will push the status flags register with bit 4('B' flag) set.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>BRK</td><td>$00</td><td>1</td><td>8</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>0
+
</td><td>1
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Forces a software interrupt using <a href="/index.php?title=IRQ2&amp;action=edit" class="new" title="IRQ2">IRQ2</a>'s vector.  Contrary to IRQs, BRK will push the status flags register with bit 4('B' flag) set.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>BRK
+
</td><td>$00
+
</td><td>1
+
</td><td>8
+
</td></tr>
+
</table>
+
 
+
 
== BSR - Branch to Subroutine ==
 
== BSR - Branch to Subroutine ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Relative</td><td>BSR $rrrr</td><td>$44</td><td>2</td><td>8</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BSR $rrrr
+
</td><td>$44
+
</td><td>2
+
</td><td>8
+
</td></tr>
+
</table>
+
 
+
 
== BVC - Branch on Overflow Clear ==
 
== BVC - Branch on Overflow Clear ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the overflow flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the overflow flag is clear, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Relative</td><td>BVC $rrrr</td><td>$50</td><td>2</td><td>2</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Relative
+
</td><td>BVC $rrrr
+
</td><td>$50
+
</td><td>2
+
 
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== BVS - Branch on Overflow Set ==
 
== BVS - Branch on Overflow Set ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
 
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>If the overflow flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
 
<p>If the overflow flag is set, branch to the address calculated from the operand.  The operand is treated as an 8-bit signed number, -128 to 127.  When
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.
+
calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction.  For example, a branch instruction with an operand of $00 will never branch.</p>
 
+
<p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).</p>
</p><p>256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Relative</td><td>BVS $rrrr</td><td>$70</td><td>2</td><td>2</td></tr></table>
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
 
+
<td>Relative
+
</td><td>BVS $rrrr
+
</td><td>$70
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== CLA - Clear Accumulator ==
 
== CLA - Clear Accumulator ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Clears the accumulator(reset to 0).</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>CLA</td><td>$62</td><td>1</td><td>2</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
 
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
 
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Clears the accumulator(reset to 0).
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
 
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLA
+
</td><td>$62
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== CLC - Clear Carry Flag ==
 
== CLC - Clear Carry Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>0</td></tr></table>
 
+
<p>Clears the carry flag.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>CLC</td><td>$18</td><td>1</td><td>2</td></tr></table>
<td><b>N</b>
+
 
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
 
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>0
+
</td></tr></table>
+
<p>Clears the carry flag.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
 
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLC
+
</td><td>$18
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== CLD - Clear Decimal Flag ==
 
== CLD - Clear Decimal Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Clears the decimal flag, disabling <a href="/index.php?title=decimal_mode&amp;action=edit" class="new" title="decimal_mode">decimal mode</a>.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>CLD</td><td>$d8</td><td>1</td><td>2</td></tr></table>
 
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
 
+
</td><td>
+
</td><td>0
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Clears the decimal flag, disabling <a href="/index.php?title=decimal_mode&amp;action=edit" class="new" title="decimal_mode">decimal mode</a>.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLD
+
</td><td>$d8
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== CLI - Clear Interrupt Flag ==
 
== CLI - Clear Interrupt Flag ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<p>Clears the interrupt flag, allowing IRQs to be processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).</p>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>CLI</td><td>$58</td><td>1</td><td>2</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Clears the interrupt flag, allowing IRQs to be processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLI
+
</td><td>$58
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
+
 
== CLV - Clear Overflow Flag ==
 
== CLV - Clear Overflow Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>0</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>CLV</td><td>$b8</td><td>1</td><td>2</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>0
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLV
+
</td><td>$b8
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
+
 
== CLX - Clear X ==
 
== CLX - Clear X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>CLX</td><td>$82</td><td>1</td><td>2</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLX
+
</td><td>$82
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
+
 
== CLY - Clear Y ==
 
== CLY - Clear Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>CLY</td><td>$c2</td><td>1</td><td>2</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CLY
+
</td><td>$c2
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
+
 
== CMP - Compare Accumulator with Memory ==
 
== CMP - Compare Accumulator with Memory ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>?</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>CMP #$ii</td><td>$c9</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>CMP $zz</td><td>$c5</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>CMP $zz,X</td><td>$d5</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>CMP $aaaa</td><td>$cd</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>CMP $aaaa,X</td><td>$dd</td><td>3</td><td>5</td></tr><tr><td>Absolute, Y</td><td>CMP $aaaa,Y</td><td>$d9</td><td>3</td><td>5</td></tr><tr><td>Indirect</td><td>CMP ($zz)</td><td>$d2</td><td>3</td><td>7</td></tr><tr><td>Indexed Indirect</td><td>CMP ($zz,X)</td><td>$c1</td><td>2</td><td>7</td></tr><tr><td>Indirect, Index</td><td>CMP ($zz),Y</td><td>$d1</td><td>2</td><td>7</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>?
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>CMP #$ii
+
</td><td>$c9
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
 
+
<td>Zero Page
+
</td><td>CMP $zz
+
</td><td>$c5
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>CMP $zz,X
+
</td><td>$d5
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>CMP $aaaa
+
</td><td>$cd
+
 
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>CMP $aaaa,X
+
</td><td>$dd
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>CMP $aaaa,Y
+
</td><td>$d9
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
 
+
<tr>
+
<td>Indirect
+
</td><td>CMP ($zz)
+
</td><td>$d2
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
</td><td>CMP ($zz,X)
+
</td><td>$c1
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indirect, Index
+
</td><td>CMP ($zz),Y
+
 
+
</td><td>$d1
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== CPX - Compare X with Memory ==
 
== CPX - Compare X with Memory ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>?</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>CPX #$ii</td><td>$e0</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>CPX $zz</td><td>$e4</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>CPX $aaaa</td><td>$ec</td><td>3</td><td>5</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>?
+
 
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
 
+
</td><td>CPX #$ii
+
</td><td>$e0
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>CPX $zz
+
</td><td>$e4
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>CPX $aaaa
+
</td><td>$ec
+
</td><td>3
+
 
+
</td><td>5
+
</td></tr>
+
</table>
+
 
== CPY - Compare Y with Memory ==
 
== CPY - Compare Y with Memory ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>?</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>CPY #$ii</td><td>$c0</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>CPY $zz</td><td>$c4</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>CPY $aaaa</td><td>$cc</td><td>3</td><td>5</td></tr>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
 
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>?
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>CPY #$ii
+
</td><td>$c0
+
 
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>CPY $zz
+
</td><td>$c4
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>CPY $aaaa
+
</td><td>$cc
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
 
+
 
</table>
 
</table>
 
== CSH - Change Speed High ==
 
== CSH - Change Speed High ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>CSH</td><td>$d4</td><td>1</td><td>3</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
 
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CSH
+
</td><td>$d4
+
</td><td>1
+
</td><td>3
+
 
+
</td></tr>
+
</table>
+
 
== CSL - Change Speed Low ==
 
== CSL - Change Speed Low ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>CSL</td><td>$54</td><td>1</td><td>3</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
 
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>CSL
+
</td><td>$54
+
</td><td>1
+
</td><td>3
+
 
+
</td></tr>
+
</table>
+
 
== DEC - Decrement ==
 
== DEC - Decrement ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Zero Page</td><td>DEC $zz</td><td>$c6</td><td>2</td><td>6</td></tr><tr><td>Zero Page, X</td><td>DEC $zz,X</td><td>$d6</td><td>2</td><td>6</td></tr><tr><td>Absolute</td><td>DEC $aaaa</td><td>$ce</td><td>3</td><td>7</td></tr><tr><td>Absolute, X</td><td>DEC $aaaa,X</td><td>$de</td><td>3</td><td>7</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
 
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>DEC $zz
+
</td><td>$c6
+
</td><td>2
+
</td><td>6
+
 
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>DEC $zz,X
+
</td><td>$d6
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>DEC $aaaa
+
</td><td>$ce
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
 
+
</td><td>DEC $aaaa,X
+
</td><td>$de
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== DEX - Decrement X ==
 
== DEX - Decrement X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>DEX</td><td>$ca</td><td>1</td><td>2</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
 
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
 
+
</td><td>DEX
+
</td><td>$ca
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== DEY - Decrement Y ==
 
== DEY - Decrement Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>DEY</td><td>$88</td><td>1</td><td>2</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
 
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
 
+
</td><td>DEY
+
</td><td>$88
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== EOR - Exclusive OR Accumulator with Memory ==
 
== EOR - Exclusive OR Accumulator with Memory ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<p>Logically <a href="/index.php/XOR" title="XOR">XOR</a> the value referenced by the operand to the accumulator.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>EOR #$ii</td><td>$49</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>EOR $zz</td><td>$45</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>EOR $zz,X</td><td>$55</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>EOR $aaaa</td><td>$4d</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>EOR $aaaa,X</td><td>$5d</td><td>3</td><td>5</td></tr><tr><td>Absolute, Y</td><td>EOR $aaaa,Y</td><td>$59</td><td>3</td><td>5</td></tr><tr><td>Indirect</td><td>EOR ($zz)</td><td>$52</td><td>3</td><td>7</td></tr><tr><td>Indexed Indirect</td><td>EOR ($zz,X)</td><td>$41</td><td>2</td><td>7</td></tr><tr><td>Indirect, Index</td><td>EOR ($zz),Y</td><td>$51</td><td>2</td><td>7</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
 
+
</td></tr></table>
+
<p>Logically <a href="/index.php/XOR" title="XOR">XOR</a> the value referenced by the operand to the accumulator.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
 
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>EOR #$ii
+
</td><td>$49
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>EOR $zz
+
</td><td>$45
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
 
+
<tr>
+
<td>Zero Page, X
+
</td><td>EOR $zz,X
+
</td><td>$55
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>EOR $aaaa
+
</td><td>$4d
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>EOR $aaaa,X
+
 
+
</td><td>$5d
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>EOR $aaaa,Y
+
</td><td>$59
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Indirect
+
</td><td>EOR ($zz)
+
</td><td>$52
+
</td><td>3
+
</td><td>7
+
 
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
</td><td>EOR ($zz,X)
+
</td><td>$41
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indirect, Index
+
</td><td>EOR ($zz),Y
+
</td><td>$51
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== INC - Increment ==
 
== INC - Increment ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<p>Increments the value of the location specified by the operand by one.  The Carry flag is not used, nor is it modified.</p>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Accumulator</td><td>INC A</td><td>$1a</td><td>1</td><td>2</td></tr><tr><td>Zero Page</td><td>INC $zz</td><td>$e6</td><td>2</td><td>6</td></tr><tr><td>Zero Page, X</td><td>INC $zz,X</td><td>$f6</td><td>2</td><td>6</td></tr><tr><td>Absolute</td><td>INC $aaaa</td><td>$ee</td><td>3</td><td>7</td></tr><tr><td>Absolute, X</td><td>INC $aaaa,X</td><td>$fe</td><td>3</td><td>7</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Increments the value of the location specified by the operand by one.  The Carry flag is not used, nor is it modified.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Accumulator
+
</td><td>INC A
+
</td><td>$1a
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
<tr>
+
 
+
<td>Zero Page
+
</td><td>INC $zz
+
</td><td>$e6
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>INC $zz,X
+
</td><td>$f6
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>INC $aaaa
+
</td><td>$ee
+
 
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>INC $aaaa,X
+
</td><td>$fe
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== INX - Increment X ==
 
== INX - Increment X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<p>Increments the value in the X register by one.  The Carry flag is not used, nor is it modified.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>INX</td><td>$e8</td><td>1</td><td>2</td></tr></table>
 
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
 
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Increments the value in the X register by one.  The Carry flag is not used, nor is it modified.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>INX
+
</td><td>$e8
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== INY - Increment Y ==
 
== INY - Increment Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<p>Increments the value in the Y register by one.  The Carry flag is not used, nor is it modified.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>INY</td><td>$c8</td><td>1</td><td>2</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Increments the value in the Y register by one.  The Carry flag is not used, nor is it modified.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>INY
+
</td><td>$c8
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== JMP - Jump ==
 
== JMP - Jump ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<p>Transfers control(sets the program counter) to the effective address calculated from the operand.</p>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Absolute</td><td>JMP $aaaa</td><td>$4c</td><td>3</td><td>4</td></tr><tr><td>Indirect</td><td>JMP ($aaaa)</td><td>$6c</td><td>3</td><td>7</td></tr><tr><td>Indexed Indirect</td><td>JMP ($aaaa,X)</td><td>$7c</td><td>3</td><td>7</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Transfers control(sets the program counter) to the effective address calculated from the operand.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>JMP $aaaa
+
</td><td>$4c
+
</td><td>3
+
</td><td>4
+
</td></tr>
+
<tr>
+
 
+
<td>Indirect
+
</td><td>JMP ($aaaa)
+
</td><td>$6c
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
</td><td>JMP ($aaaa,X)
+
</td><td>$7c
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== JSR - Jump to Subroutine ==
 
== JSR - Jump to Subroutine ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Absolute</td><td>JSR $aaaa</td><td>$20</td><td>3</td><td>7</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>JSR $aaaa
+
</td><td>$20
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== LDA - Load Accumulator ==
 
== LDA - Load Accumulator ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<p>Loads the accumulator with the value at the effective address.</p>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>LDA #$ii</td><td>$a9</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>LDA $zz</td><td>$a5</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>LDA $zz,X</td><td>$b5</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>LDA $aaaa</td><td>$ad</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>LDA $aaaa,X</td><td>$bd</td><td>3</td><td>5</td></tr><tr><td>Absolute, Y</td><td>LDA $aaaa,Y</td><td>$b9</td><td>3</td><td>5</td></tr><tr><td>Indirect</td><td>LDA ($zz)</td><td>$b2</td><td>3</td><td>7</td></tr><tr><td>Indexed Indirect</td><td>LDA ($zz,X)</td><td>$a1</td><td>2</td><td>7</td></tr><tr><td>Indirect, Index</td><td>LDA ($zz),Y</td><td>$b1</td><td>2</td><td>7</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Loads the accumulator with the value at the effective address.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>LDA #$ii
+
</td><td>$a9
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
 
+
<td>Zero Page
+
</td><td>LDA $zz
+
</td><td>$a5
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>LDA $zz,X
+
</td><td>$b5
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>LDA $aaaa
+
</td><td>$ad
+
 
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>LDA $aaaa,X
+
</td><td>$bd
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>LDA $aaaa,Y
+
</td><td>$b9
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
 
+
<tr>
+
<td>Indirect
+
</td><td>LDA ($zz)
+
</td><td>$b2
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
</td><td>LDA ($zz,X)
+
</td><td>$a1
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indirect, Index
+
</td><td>LDA ($zz),Y
+
 
+
</td><td>$b1
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== LDX - Load X ==
 
== LDX - Load X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<p>Loads the X register with the value at the effective address.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>LDX #$ii</td><td>$a2</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>LDX $zz</td><td>$a6</td><td>2</td><td>4</td></tr><tr><td>Zero Page, Y</td><td>LDX $zz,Y</td><td>$b6</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>LDX $aaaa</td><td>$ae</td><td>3</td><td>5</td></tr><tr><td>Absolute, Y</td><td>LDX $aaaa,Y</td><td>$be</td><td>3</td><td>5</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
 
+
</td></tr></table>
+
<p>Loads the X register with the value at the effective address.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
 
+
<tr>
+
<td>Immediate
+
</td><td>LDX #$ii
+
</td><td>$a2
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>LDX $zz
+
</td><td>$a6
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, Y
+
</td><td>LDX $zz,Y
+
 
+
</td><td>$b6
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>LDX $aaaa
+
</td><td>$ae
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>LDX $aaaa,Y
+
</td><td>$be
+
</td><td>3
+
</td><td>5
+
 
+
</td></tr>
+
</table>
+
 
== LDY - Load Y ==
 
== LDY - Load Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<p>Loads the Y register with the value at the effective address.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>LDY #$ii</td><td>$a0</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>LDY $zz</td><td>$a4</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>LDY $zz,X</td><td>$b4</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>LDY $aaaa</td><td>$ac</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>LDY $aaaa,X</td><td>$bc</td><td>3</td><td>5</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Loads the Y register with the value at the effective address.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>LDY #$ii
+
</td><td>$a0
+
 
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>LDY $zz
+
</td><td>$a4
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>LDY $zz,X
+
</td><td>$b4
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
 
+
<tr>
+
<td>Absolute
+
</td><td>LDY $aaaa
+
</td><td>$ac
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>LDY $aaaa,X
+
</td><td>$bc
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
</table>
+
 
== LSR - Logical Shift Right ==
 
== LSR - Logical Shift Right ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>0</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Accumulator</td><td>LSR A</td><td>$4a</td><td>1</td><td>2</td></tr><tr><td>Zero Page</td><td>LSR $zz</td><td>$46</td><td>2</td><td>6</td></tr><tr><td>Zero Page, X</td><td>LSR $zz,X</td><td>$56</td><td>2</td><td>6</td></tr><tr><td>Absolute</td><td>LSR $aaaa</td><td>$4e</td><td>3</td><td>7</td></tr><tr><td>Absolute, X</td><td>LSR $aaaa,X</td><td>$5e</td><td>3</td><td>7</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>0
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Accumulator
+
</td><td>LSR A
+
</td><td>$4a
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>LSR $zz
+
 
+
</td><td>$46
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>LSR $zz,X
+
</td><td>$56
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>LSR $aaaa
+
</td><td>$4e
+
</td><td>3
+
</td><td>7
+
 
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>LSR $aaaa,X
+
</td><td>$5e
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== NOP - No Operation ==
 
== NOP - No Operation ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>NOP</td><td>$ea</td><td>1</td><td>2</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
 
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
 
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
 
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>NOP
+
</td><td>$ea
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== ORA - OR Accumulator with Memory ==
 
== ORA - OR Accumulator with Memory ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<p>Logically <a href="/index.php?title=OR&amp;action=edit" class="new" title="OR">OR</a> the value referenced by the operand with the accumulator, storing the result in the accumulator.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>ORA #$ii</td><td>$09</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>ORA $zz</td><td>$05</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>ORA $zz,X</td><td>$15</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>ORA $aaaa</td><td>$0d</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>ORA $aaaa,X</td><td>$1d</td><td>3</td><td>5</td></tr><tr><td>Absolute, Y</td><td>ORA $aaaa,Y</td><td>$19</td><td>3</td><td>5</td></tr><tr><td>Indirect</td><td>ORA ($zz)</td><td>$12</td><td>3</td><td>7</td></tr><tr><td>Indexed Indirect</td><td>ORA ($zz,X)</td><td>$01</td><td>2</td><td>7</td></tr><tr><td>Indirect, Index</td><td>ORA ($zz),Y</td><td>$11</td><td>2</td><td>7</td></tr></table>
<td><b>N</b>
+
 
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
 
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Logically <a href="/index.php?title=OR&amp;action=edit" class="new" title="OR">OR</a> the value referenced by the operand with the accumulator, storing the result in the accumulator.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>ORA #$ii
+
</td><td>$09
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>ORA $zz
+
 
+
</td><td>$05
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>ORA $zz,X
+
</td><td>$15
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>ORA $aaaa
+
</td><td>$0d
+
</td><td>3
+
</td><td>5
+
 
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>ORA $aaaa,X
+
</td><td>$1d
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>ORA $aaaa,Y
+
</td><td>$19
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Indirect
+
 
+
</td><td>ORA ($zz)
+
</td><td>$12
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
</td><td>ORA ($zz,X)
+
</td><td>$01
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indirect, Index
+
</td><td>ORA ($zz),Y
+
</td><td>$11
+
</td><td>2
+
 
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== PHA - Push A ==
 
== PHA - Push A ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Pushes the accumulator to the stack.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>PHA</td><td>$48</td><td>1</td><td>3</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
 
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Pushes the accumulator to the stack.
+
 
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
 
+
</td><td>PHA
+
</td><td>$48
+
</td><td>1
+
</td><td>3
+
</td></tr>
+
</table>
+
 
== PHP - Push P ==
 
== PHP - Push P ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Pushes the status flags(1 byte) to the stack.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>PHP</td><td>$08</td><td>1</td><td>3</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
 
+
</td></tr></table>
+
<p>Pushes the status flags(1 byte) to the stack.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
 
+
<tr>
+
<td>Implied
+
</td><td>PHP
+
</td><td>$08
+
</td><td>1
+
</td><td>3
+
</td></tr>
+
</table>
+
 
== PHX - Push X ==
 
== PHX - Push X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Pushes the X register to the stack.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>PHX</td><td>$da</td><td>1</td><td>3</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
 
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
 
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Pushes the X register to the stack.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
 
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>PHX
+
</td><td>$da
+
</td><td>1
+
</td><td>3
+
</td></tr>
+
</table>
+
 
== PHY - Push Y ==
 
== PHY - Push Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Pushes the Y register to the stack.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>PHY</td><td>$5a</td><td>1</td><td>3</td></tr></table>
<td><b>N</b>
+
 
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
 
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Pushes the Y register to the stack.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
 
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>PHY
+
</td><td>$5a
+
</td><td>1
+
</td><td>3
+
</td></tr>
+
</table>
+
 
== PLA - Pull A ==
 
== PLA - Pull A ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<p>Pulls a value off the stack, and stores the value in the accumulator.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>PLA</td><td>$68</td><td>1</td><td>4</td></tr></table>
 
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
 
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Pulls a value off the stack, and stores the value in the accumulator.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>PLA
+
</td><td>$68
+
</td><td>1
+
</td><td>4
+
</td></tr>
+
</table>
+
 
== PLP - Pull P ==
 
== PLP - Pull P ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>?</td><td>?</td><td>?</td><td>?</td><td>?</td><td>?</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>PLP</td><td>$28</td><td>1</td><td>4</td></tr></table>
<tr style="background: #efefef">
+
<p><br /></p>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>?
+
</td><td>?
+
</td><td>?
+
</td><td>?
+
</td><td>?
+
</td><td>?
+
</td><td>?
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>PLP
+
</td><td>$28
+
</td><td>1
+
</td><td>4
+
</td></tr>
+
</table>
+
<p><br />
+
</p>
+
 
== PLX - Pull X ==
 
== PLX - Pull X ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<p>Pulls a value off the stack, and stores the value in the X register.</p>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>PLX</td><td>$fa</td><td>1</td><td>4</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Pulls a value off the stack, and stores the value in the X register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>PLX
+
</td><td>$fa
+
</td><td>1
+
</td><td>4
+
</td></tr>
+
</table>
+
 
+
 
== PLY - Pull Y ==
 
== PLY - Pull Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<p>Pulls a value off the stack, and stores the value in Y register.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>PLY</td><td>$7a</td><td>1</td><td>4</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Pulls a value off the stack, and stores the value in Y register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
 
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>PLY
+
</td><td>$7a
+
</td><td>1
+
</td><td>4
+
 
+
</td></tr>
+
</table>
+
 
== RMBn - Reset Memory Bit n ==
 
== RMBn - Reset Memory Bit n ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Reads the zero-page address specified by the operand, resets(clears) the bit "n", and then writes it back to the aforementioned address.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Zero Page</td><td>RMB0 $zz</td><td>$07</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>RMB1 $zz</td><td>$17</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>RMB2 $zz</td><td>$27</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>RMB3 $zz</td><td>$37</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>RMB4 $zz</td><td>$47</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>RMB5 $zz</td><td>$57</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>RMB6 $zz</td><td>$67</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>RMB7 $zz</td><td>$77</td><td>2</td><td>7</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Reads the zero-page address specified by the operand, resets(clears) the bit "n", and then writes it back to the aforementioned address.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB0 $zz
+
</td><td>$07
+
 
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB1 $zz
+
</td><td>$17
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB2 $zz
+
</td><td>$27
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
 
+
<tr>
+
<td>Zero Page
+
</td><td>RMB3 $zz
+
</td><td>$37
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB4 $zz
+
</td><td>$47
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB5 $zz
+
 
+
</td><td>$57
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB6 $zz
+
</td><td>$67
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>RMB7 $zz
+
</td><td>$77
+
</td><td>2
+
</td><td>7
+
 
+
</td></tr>
+
</table>
+
 
== ROL - Rotate Left ==
 
== ROL - Rotate Left ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>?</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Accumulator</td><td>ROL A</td><td>$2a</td><td>1</td><td>2</td></tr><tr><td>Zero Page</td><td>ROL $zz</td><td>$26</td><td>2</td><td>6</td></tr><tr><td>Zero Page, X</td><td>ROL $zz,X</td><td>$36</td><td>2</td><td>6</td></tr><tr><td>Absolute</td><td>ROL $aaaa</td><td>$2e</td><td>3</td><td>7</td></tr><tr><td>Absolute, X</td><td>ROL $aaaa,X</td><td>$3e</td><td>3</td><td>7</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>?
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
 
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Accumulator
+
</td><td>ROL A
+
</td><td>$2a
+
</td><td>1
+
</td><td>2
+
 
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>ROL $zz
+
</td><td>$26
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>ROL $zz,X
+
</td><td>$36
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Absolute
+
 
+
</td><td>ROL $aaaa
+
</td><td>$2e
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>ROL $aaaa,X
+
</td><td>$3e
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== ROR - Rotate Right ==
 
== ROR - Rotate Right ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>?</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Accumulator</td><td>ROR A</td><td>$6a</td><td>1</td><td>2</td></tr><tr><td>Zero Page</td><td>ROR $zz</td><td>$66</td><td>2</td><td>6</td></tr><tr><td>Zero Page, X</td><td>ROR $zz,X</td><td>$76</td><td>2</td><td>6</td></tr><tr><td>Absolute</td><td>ROR $aaaa</td><td>$6e</td><td>3</td><td>7</td></tr><tr><td>Absolute, X</td><td>ROR $aaaa,X</td><td>$7e</td><td>3</td><td>7</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>?
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Accumulator
+
</td><td>ROR A
+
</td><td>$6a
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>ROR $zz
+
</td><td>$66
+
</td><td>2
+
 
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>ROR $zz,X
+
</td><td>$76
+
</td><td>2
+
</td><td>6
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>ROR $aaaa
+
</td><td>$6e
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
 
+
<td>Absolute, X
+
</td><td>ROR $aaaa,X
+
</td><td>$7e
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== RTI - Return from Interrupt ==
 
== RTI - Return from Interrupt ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>?</td><td>?</td><td>?</td><td>?</td><td>?</td><td>?</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>RTI</td><td>$40</td><td>1</td><td>7</td></tr></table>
<tr style="background: #efefef">
+
<p><br /></p>
<td><b>N</b>
+
</td><td><b>V</b>
+
 
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>?
+
</td><td>?
+
</td><td>?
+
</td><td>?
+
 
+
</td><td>?
+
</td><td>?
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
 
+
<tr>
+
<td>Implied
+
</td><td>RTI
+
</td><td>$40
+
</td><td>1
+
</td><td>7
+
</td></tr>
+
</table>
+
<p><br />
+
</p>
+
 
== RTS - Return from Subroutine ==
 
== RTS - Return from Subroutine ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>RTS</td><td>$60</td><td>1</td><td>7</td></tr></table>
<tr style="background: #efefef">
+
<p><br /></p>
<td><b>N</b>
+
 
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
 
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
 
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>RTS
+
</td><td>$60
+
</td><td>1
+
</td><td>7
+
</td></tr>
+
</table>
+
<p><br />
+
</p>
+
 
== SAX - Swap A and X ==
 
== SAX - Swap A and X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Swaps the values in the accumulator and X register.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>SAX</td><td>$22</td><td>1</td><td>3</td></tr></table>
 
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
 
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Swaps the values in the accumulator and X register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>SAX
+
</td><td>$22
+
</td><td>1
+
</td><td>3
+
</td></tr>
+
</table>
+
 
== SAY - Swap A and Y ==
 
== SAY - Swap A and Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Swap the values in the accumulator and Y register.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>SAY</td><td>$42</td><td>1</td><td>3</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Swap the values in the accumulator and Y register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>SAY
+
</td><td>$42
+
</td><td>1
+
</td><td>3
+
</td></tr>
+
</table>
+
 
== SBC - Subtract with Borrow ==
 
== SBC - Subtract with Borrow ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>?</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>?</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).</p>
 
+
<p>The overflow flag is not affected by this instruction if in Decimal mode.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>SBC #$ii</td><td>$e9</td><td>2</td><td>2</td></tr><tr><td>Zero Page</td><td>SBC $zz</td><td>$e5</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>SBC $zz,X</td><td>$f5</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>SBC $aaaa</td><td>$ed</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>SBC $aaaa,X</td><td>$fd</td><td>3</td><td>5</td></tr><tr><td>Absolute, Y</td><td>SBC $aaaa,Y</td><td>$f9</td><td>3</td><td>5</td></tr><tr><td>Indirect</td><td>SBC ($zz)</td><td>$f2</td><td>3</td><td>7</td></tr><tr><td>Indexed Indirect</td><td>SBC ($zz,X)</td><td>$e1</td><td>2</td><td>7</td></tr><tr><td>Indirect, Index</td><td>SBC ($zz),Y</td><td>$f1</td><td>2</td><td>7</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>?
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>?
+
</td></tr></table>
+
<p>If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).
+
</p><p>The overflow flag is not affected by this instruction if in Decimal mode.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>SBC #$ii
+
</td><td>$e9
+
</td><td>2
+
</td><td>2
+
</td></tr>
+
<tr>
+
 
+
<td>Zero Page
+
</td><td>SBC $zz
+
</td><td>$e5
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>SBC $zz,X
+
</td><td>$f5
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>SBC $aaaa
+
</td><td>$ed
+
 
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>SBC $aaaa,X
+
</td><td>$fd
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>SBC $aaaa,Y
+
</td><td>$f9
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
 
+
<tr>
+
<td>Indirect
+
</td><td>SBC ($zz)
+
</td><td>$f2
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
</td><td>SBC ($zz,X)
+
</td><td>$e1
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indirect, Index
+
</td><td>SBC ($zz),Y
+
 
+
</td><td>$f1
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== SEC - Set Carry Flag ==
 
== SEC - Set Carry Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>1</td></tr></table>
 
+
<p>Sets the carry flag.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>SEC</td><td>$38</td><td>1</td><td>2</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>1
+
 
+
</td></tr></table>
+
<p>Sets the carry flag.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
 
+
<tr>
+
<td>Implied
+
</td><td>SEC
+
</td><td>$38
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== SED - Set Decimal Flag ==
 
== SED - Set Decimal Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>1</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Sets the decimal flag, enabling <a href="/index.php?title=decimal_mode&amp;action=edit" class="new" title="decimal_mode">decimal mode</a>.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>SED</td><td>$f8</td><td>1</td><td>2</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
 
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>1
+
</td><td>
+
 
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Sets the decimal flag, enabling <a href="/index.php?title=decimal_mode&amp;action=edit" class="new" title="decimal_mode">decimal mode</a>.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
 
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>SED
+
</td><td>$f8
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== SEI - Set Interrupt Flag ==
 
== SEI - Set Interrupt Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>1</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Sets the interrupt flag, preventing IRQs from being processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>SEI</td><td>$78</td><td>1</td><td>2</td></tr></table>
 
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
 
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>1
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Sets the interrupt flag, preventing IRQs from being processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>SEI
+
</td><td>$78
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== SET - Set T Flag ==
 
== SET - Set T Flag ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>1</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Sets the T flag, which changes the behavior of the next instruction if the next instruction is ADC, AND, EOR, ORA, or SBC, in which case the operation is performed on the zero-page address specified by the X register, instead of the accumulator.</p>
<tr style="background: #efefef">
+
<p>Note that interrupt processing preserves the T-flag, and clears the T-flag in the interrupt handler, so a programmer needn't worry about an interrupt
<td><b>N</b>
+
occuring between SET and the next instruction.</p>
</td><td><b>V</b>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>SET</td><td>$f4</td><td>1</td><td>2</td></tr></table>
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>
+
</td><td>
+
</td><td>1
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Sets the T flag, which changes the behavior of the next instruction if the next instruction is ADC, AND, EOR, ORA, or SBC, in which case the operation is performed on the zero-page address specified by the X register, instead of the accumulator.
+
</p><p>Note that interrupt processing preserves the T-flag, and clears the T-flag in the interrupt handler, so a programmer needn't worry about an interrupt
+
occuring between SET and the next instruction.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>SET
+
</td><td>$f4
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
+
 
== SMBn - Set Memory Bit n ==
 
== SMBn - Set Memory Bit n ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Reads the zero-page address specified by the operand, sets the bit "n", and then writes it back to the aforementioned address.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Zero Page</td><td>SMB0 $zz</td><td>$87</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>SMB1 $zz</td><td>$97</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>SMB2 $zz</td><td>$a7</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>SMB3 $zz</td><td>$b7</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>SMB4 $zz</td><td>$c7</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>SMB5 $zz</td><td>$d7</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>SMB6 $zz</td><td>$e7</td><td>2</td><td>7</td></tr><tr><td>Zero Page</td><td>SMB7 $zz</td><td>$f7</td><td>2</td><td>7</td></tr>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Reads the zero-page address specified by the operand, sets the bit "n", and then writes it back to the aforementioned address.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
 
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>SMB0 $zz
+
</td><td>$87
+
</td><td>2
+
</td><td>7
+
 
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>SMB1 $zz
+
</td><td>$97
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>SMB2 $zz
+
</td><td>$a7
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
 
+
</td><td>SMB3 $zz
+
</td><td>$b7
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>SMB4 $zz
+
</td><td>$c7
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>SMB5 $zz
+
</td><td>$d7
+
</td><td>2
+
 
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>SMB6 $zz
+
</td><td>$e7
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>SMB7 $zz
+
</td><td>$f7
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
 
+
 
</table>
 
</table>
 
== ST0 - Store <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> No. 0 ==
 
== ST0 - Store <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> No. 0 ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Writes the immediate value to the physical address $1FE000, the <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a>'s address register.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>ST0 #$ii</td><td>$03</td><td>2</td><td>5</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
 
+
</td></tr></table>
+
<p>Writes the immediate value to the physical address $1FE000, the <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a>'s address register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
 
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>ST0 #$ii
+
</td><td>$03
+
</td><td>2
+
</td><td>5
+
</td></tr>
+
</table>
+
 
== ST1 - Store <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> No. 1 ==
 
== ST1 - Store <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> No. 1 ==
 
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<p>Writes the immediate value to the physical address $1FE002, the <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a>'s lower data register.</p>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>ST1 #$ii</td><td>$13</td><td>2</td><td>5</td></tr></table>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
 
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Writes the immediate value to the physical address $1FE002, the <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a>'s lower data register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>ST1 #$ii
+
</td><td>$13
+
</td><td>2
+
 
+
</td><td>5
+
</td></tr>
+
</table>
+
 
== ST2 - Store <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> No. 2 ==
 
== ST2 - Store <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> No. 2 ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Writes the immediate value to the physical address $1FE003, the <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a>'s upper data register.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>ST2 #$ii</td><td>$23</td><td>2</td><td>5</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
 
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
 
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Writes the immediate value to the physical address $1FE003, the <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a>'s upper data register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>ST2 #$ii
+
</td><td>$23
+
</td><td>2
+
</td><td>5
+
</td></tr>
+
</table>
+
 
== STA - Store Accumulator ==
 
== STA - Store Accumulator ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Stores the value in the accumulator to the effective address specified by the operand.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Zero Page</td><td>STA $zz</td><td>$85</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>STA $zz,X</td><td>$95</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>STA $aaaa</td><td>$8d</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>STA $aaaa,X</td><td>$9d</td><td>3</td><td>5</td></tr><tr><td>Absolute, Y</td><td>STA $aaaa,Y</td><td>$99</td><td>3</td><td>5</td></tr><tr><td>Indirect</td><td>STA ($zz)</td><td>$92</td><td>3</td><td>7</td></tr><tr><td>Indexed Indirect</td><td>STA ($zz,X)</td><td>$81</td><td>2</td><td>7</td></tr><tr><td>Indirect, Index</td><td>STA ($zz),Y</td><td>$91</td><td>2</td><td>7</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Stores the value in the accumulator to the effective address specified by the operand.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>STA $zz
+
</td><td>$85
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>STA $zz,X
+
 
+
</td><td>$95
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>STA $aaaa
+
</td><td>$8d
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>STA $aaaa,X
+
</td><td>$9d
+
</td><td>3
+
</td><td>5
+
 
+
</td></tr>
+
<tr>
+
<td>Absolute, Y
+
</td><td>STA $aaaa,Y
+
</td><td>$99
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Indirect
+
</td><td>STA ($zz)
+
</td><td>$92
+
</td><td>3
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indexed Indirect
+
 
+
</td><td>STA ($zz,X)
+
</td><td>$81
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
<tr>
+
<td>Indirect, Index
+
</td><td>STA ($zz),Y
+
</td><td>$91
+
</td><td>2
+
</td><td>7
+
</td></tr>
+
</table>
+
 
== STX - Store X ==
 
== STX - Store X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Stores the value in the X register to the effective address specified by the operand.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Zero Page</td><td>STX $zz</td><td>$86</td><td>2</td><td>4</td></tr><tr><td>Zero Page, Y</td><td>STX $zz,Y</td><td>$96</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>STX $aaaa</td><td>$8e</td><td>3</td><td>5</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Stores the value in the X register to the effective address specified by the operand.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>STX $zz
+
</td><td>$86
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, Y
+
</td><td>STX $zz,Y
+
 
+
</td><td>$96
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>STX $aaaa
+
</td><td>$8e
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
</table>
+
 
== STY - Store Y ==
 
== STY - Store Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Stores the value in the Y register to the effective address specified by the operand.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Zero Page</td><td>STY $zz</td><td>$84</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>STY $zz,X</td><td>$94</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>STY $aaaa</td><td>$8c</td><td>3</td><td>5</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
 
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Stores the value in the Y register to the effective address specified by the operand.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>STY $zz
+
</td><td>$84
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>STY $zz,X
+
 
+
</td><td>$94
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>STY $aaaa
+
</td><td>$8c
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
</table>
+
 
== STZ - Store Zero ==
 
== STZ - Store Zero ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Stores zero to the effective address specified by the operand.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Zero Page</td><td>STZ $zz</td><td>$64</td><td>2</td><td>4</td></tr><tr><td>Zero Page, X</td><td>STZ $zz,X</td><td>$74</td><td>2</td><td>4</td></tr><tr><td>Absolute</td><td>STZ $aaaa</td><td>$9c</td><td>3</td><td>5</td></tr><tr><td>Absolute, X</td><td>STZ $aaaa,X</td><td>$9e</td><td>3</td><td>5</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
 
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Stores zero to the effective address specified by the operand.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
 
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Zero Page
+
</td><td>STZ $zz
+
</td><td>$64
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Zero Page, X
+
</td><td>STZ $zz,X
+
 
+
</td><td>$74
+
</td><td>2
+
</td><td>4
+
</td></tr>
+
<tr>
+
<td>Absolute
+
</td><td>STZ $aaaa
+
</td><td>$9c
+
</td><td>3
+
</td><td>5
+
</td></tr>
+
<tr>
+
<td>Absolute, X
+
</td><td>STZ $aaaa,X
+
</td><td>$9e
+
</td><td>3
+
</td><td>5
+
 
+
</td></tr>
+
</table>
+
 
== SXY - Swap X and Y ==
 
== SXY - Swap X and Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Swaps the values in the X register and the Y register.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>SXY</td><td>$02</td><td>1</td><td>3</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Swaps the values in the X register and the Y register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
</td><td>SXY
+
</td><td>$02
+
 
+
</td><td>1
+
</td><td>3
+
</td></tr>
+
</table>
+
 
== TAI - Transfer Alternate Increment ==
 
== TAI - Transfer Alternate Increment ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
 
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):
+
 
+
</p>
+
 
<pre>Alternate = 0
 
<pre>Alternate = 0
 
Do
 
Do
Line 4,193: Line 320:
 
  llll = llll - 1
 
  llll = llll - 1
 
  Alternate = Alternate ^ 1
 
  Alternate = Alternate ^ 1
While llll&nbsp;!= 0
+
While llll&nbsp;!= 0</pre>
</pre>
+
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
will be effectively treated as a length of "65536".
+
will be effectively treated as a length of "65536".</p>
</p><p>Please note that the cycles-per-byte-transferred will be higher if <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> registers are used as source and/or destination.
+
<p>Please note that the cycles-per-byte-transferred will be higher if <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> registers are used as source and/or destination.</p>
</p><p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer
+
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer
is complete.
+
is complete.</p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Block Transfer</td><td>TAI $ssss, $dddd, $llll</td><td>$f3</td><td>7</td><td>17 + 6 * llll</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Block Transfer
+
</td><td>TAI $ssss, $dddd, $llll
+
</td><td>$f3
+
</td><td>7
+
</td><td>17 + 6 * llll
+
</td></tr>
+
</table>
+
 
+
 
== TAM - Transfer Accumulator to <a href="/index.php?title=MPR&amp;action=edit" class="new" title="MPR">MPRs</a> ==
 
== TAM - Transfer Accumulator to <a href="/index.php?title=MPR&amp;action=edit" class="new" title="MPR">MPRs</a> ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
 
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p>Copies the value in the accumulator to each MPR with the corresponding bit set in the immediate operand, eg. TAM #$41 will load MPR0 and MPR6 with the
 
<p>Copies the value in the accumulator to each MPR with the corresponding bit set in the immediate operand, eg. TAM #$41 will load MPR0 and MPR6 with the
value in the accumulator.  If no bits are set, no transfer will occur, and the instruction is effectively a 5-cycle NOP.
+
value in the accumulator.  If no bits are set, no transfer will occur, and the instruction is effectively a 5-cycle NOP.</p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>TAM #$ii</td><td>$53</td><td>2</td><td>5</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Immediate
+
</td><td>TAM #$ii
+
</td><td>$53
+
 
+
</td><td>2
+
</td><td>5
+
</td></tr>
+
</table>
+
 
== TAX - Transfer Accumulator to X ==
 
== TAX - Transfer Accumulator to X ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<p>Copies the value of the accumulator to the X register.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>TAX</td><td>$aa</td><td>1</td><td>2</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
 
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
</td></tr></table>
+
<p>Copies the value of the accumulator to the X register.
+
 
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Implied
+
 
+
</td><td>TAX
+
</td><td>$aa
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== TAY - Transfer Accumulator to Y ==
 
== TAY - Transfer Accumulator to Y ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>?</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>?</td><td>&nbsp;</td></tr></table>
 
+
<p>Copies the value of the accumulator to the Y register.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Implied</td><td>TAY</td><td>$a8</td><td>1</td><td>2</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>?
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>?
+
</td><td>
+
 
+
</td></tr></table>
+
<p>Copies the value of the accumulator to the Y register.
+
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
 
+
<tr>
+
<td>Implied
+
</td><td>TAY
+
</td><td>$a8
+
</td><td>1
+
</td><td>2
+
</td></tr>
+
</table>
+
 
== TDD - Transfer Decrement Decrement ==
 
== TDD - Transfer Decrement Decrement ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
 
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
 
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):
+
</p>
+
 
<pre>Do
 
<pre>Do
 
  Value = Read(ssss)
 
  Value = Read(ssss)
Line 4,380: Line 349:
 
  dddd = dddd - 1
 
  dddd = dddd - 1
 
  llll = llll - 1
 
  llll = llll - 1
While llll&nbsp;!= 0
+
While llll&nbsp;!= 0</pre>
</pre>
+
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
will be effectively treated as a length of "65536".
+
will be effectively treated as a length of "65536".</p>
</p><p>Please note that the cycles-per-byte-transferred will be higher if <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> registers are used as source and/or destination.
+
<p>Please note that the cycles-per-byte-transferred will be higher if <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> registers are used as source and/or destination.</p>
</p><p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.
+
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Block Transfer</td><td>TDD $ssss, $dddd, $llll</td><td>$c3</td><td>7</td><td>17 + 6 * llll</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Block Transfer
+
</td><td>TDD $ssss, $dddd, $llll
+
</td><td>$c3
+
 
+
</td><td>7
+
</td><td>17 + 6 * llll
+
</td></tr>
+
</table>
+
 
== TIA - Transfer Increment Alternate ==
 
== TIA - Transfer Increment Alternate ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
 
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
 
<p><br />
 
<p><br />
 
+
Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):
+
</p>
+
 
<pre>Alternate = 0
 
<pre>Alternate = 0
 
Do
 
Do
Line 4,438: Line 366:
 
  llll = llll - 1
 
  llll = llll - 1
 
  Alternate = Alternate ^ 1
 
  Alternate = Alternate ^ 1
While llll&nbsp;!= 0
+
While llll&nbsp;!= 0</pre>
</pre>
+
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
will be effectively treated as a length of "65536".
+
will be effectively treated as a length of "65536".</p>
</p><p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.
+
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
</p><p>Please note that the cycles-per-byte-transferred will be higher if <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> registers are used as source and/or destination.
+
<p>Please note that the cycles-per-byte-transferred will be higher if <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> registers are used as source and/or destination.</p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Block Transfer</td><td>TIA $ssss, $dddd, $llll</td><td>$e3</td><td>7</td><td>17 + 6 * llll</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
 
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Block Transfer
+
</td><td>TIA $ssss, $dddd, $llll
+
</td><td>$e3
+
</td><td>7
+
</td><td>17 + 6 * llll
+
</td></tr>
+
</table>
+
 
+
 
== TII - Transfer Increment Increment ==
 
== TII - Transfer Increment Increment ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
 
+
</td><td><b>C</b>
+
</td></tr>
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):
+
</p>
+
 
<pre>Do
 
<pre>Do
 
  Value = Read(ssss)
 
  Value = Read(ssss)
Line 4,494: Line 381:
 
  dddd = dddd + 1
 
  dddd = dddd + 1
 
  llll = llll - 1
 
  llll = llll - 1
While llll&nbsp;!= 0
+
While llll&nbsp;!= 0</pre>
</pre>
+
 
+
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
will be effectively treated as a length of "65536".
+
will be effectively treated as a length of "65536".</p>
</p><p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.
+
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
</p><p>Please note that the cycles-per-byte-transferred will be higher if <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> registers are used as source and/or destination.
+
<p>Please note that the cycles-per-byte-transferred will be higher if <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> registers are used as source and/or destination.</p>
</p>
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Block Transfer</td><td>TII $ssss, $dddd, $llll</td><td>$73</td><td>7</td><td>17 + 6 * llll</td></tr></table>
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
 
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Block Transfer
+
</td><td>TII $ssss, $dddd, $llll
+
</td><td>$73
+
</td><td>7
+
</td><td>17 + 6 * llll
+
</td></tr>
+
</table>
+
 
== TIN - Transfer Increment ==
 
== TIN - Transfer Increment ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):</p>
<tr style="background: #efefef">
+
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td></tr>
+
 
+
<tr>
+
<td>
+
</td><td>
+
</td><td>0
+
</td><td>
+
</td><td>
+
</td><td>
+
</td><td>
+
</td></tr></table>
+
<p>Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):
+
</p>
+
 
<pre>Do
 
<pre>Do
 
  Value = Read(ssss)
 
  Value = Read(ssss)
Line 4,549: Line 395:
 
  ssss = ssss + 1
 
  ssss = ssss + 1
 
  llll = llll - 1
 
  llll = llll - 1
While llll&nbsp;!= 0
+
While llll&nbsp;!= 0</pre>
</pre>
+
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
 
<p>It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0"
will be effectively treated as a length of "65536".
+
will be effectively treated as a length of "65536".</p>
</p><p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.
+
<p>All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.</p>
</p><p>Please note that the cycles-per-byte-transferred will be higher if <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> registers are used as source and/or destination.
+
<p>Please note that the cycles-per-byte-transferred will be higher if <a href="/index.php/HuC6270" title="HuC6270"> (HuC6270) VDC</a> registers are used as source and/or destination.</p>
 
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Block Transfer</td><td>TIN $ssss, $dddd, $llll</td><td>$d3</td><td>7</td><td>17 + 6 * llll</td></tr></table>
</p>
+
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
 
+
<tr style="background: #efefef">
+
<td><b>Addressing Mode</b>
+
</td><td><b>Syntax</b>
+
</td><td><b>Opcode</b>
+
</td><td><b>Bytes</b>
+
</td><td><b>Cycles</b>
+
</td></tr>
+
<tr>
+
<td>Block Transfer
+
 
+
</td><td>TIN $ssss, $dddd, $llll
+
</td><td>$d3
+
</td><td>7
+
</td><td>17 + 6 * llll
+
</td></tr>
+
</table>
+
 
== TMA - Transfer MPR to Accumulator ==
 
== TMA - Transfer MPR to Accumulator ==
<table border="1" cellpadding="5" cellspacing="1" style="border-collapse: collapse">
+
<table><tr><td><b>N</b></td><td><b>V</b></td><td><b>T</b></td><td><b>D</b></td><td><b>I</b></td><td><b>Z</b></td><td><b>C</b></td></tr><tr><td>&nbsp;</td><td>&nbsp;</td><td>0</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td><td>&nbsp;</td></tr></table>
 
+
<p>Copies the value in the MPR, specified by the corresponding bit being set in the immediate operand, to the accumulator.  If an immediate value of $00 is used, the accumulator will be loaded with the last value transfered by TAM(note that if an immediate value of $00 is used with TAM, no transfer occurs, and as such won't be read back if an immediate value of $00 is used with TMA).  Undefined behavior results if multiple bits are set.</p>
<tr style="background: #efefef">
+
<table><tr><td><b>Addressing Mode</b></td><td><b>Syntax</b></td><td><b>Opcode</b></td><td><b>Bytes</b></td><td><b>Cycles</b></td></tr><tr><td>Immediate</td><td>TMA #$ii</td><td>$43</td><td>2</td><td>4</td></tr></table>
<td><b>N</b>
+
</td><td><b>V</b>
+
</td><td><b>T</b>
+
 
+
</td><td><b>D</b>
+
</td><td><b>I</b>
+
</td><td><b>Z</b>
+
</td><td><b>C</b>
+
</td>&