HuC6280 Instruction Set

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ADC - Add with Carry

NVTDIZC
??0  ??

Add the value specified by the operand, and 1 if the Carry flag is set, to the value in the accumulator. If the result is too large to fit in the accumulator, the carry flag will be set, otherwise it will be cleared.

If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).

The overflow flag is not affected by this instruction if in Decimal mode; otherwise, if bit7 of the result != bit7 of the accumulator before the operation, and bit7 of the accumulator before the operation == bit7 of the value specified by the operand, the overflow flag is set, otherwise it is cleared. In other words, if we were to treat the accumulator and value specified by the operand as two's complement numbers, in the range of -128 to 127, the overflow flag will be set if the end result is outside of this range(otherwise it will be cleared).

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateADC #$ii$6922
Zero PageADC $zz$6524
Zero Page, XADC $zz,X$7524
AbsoluteADC $aaaa$6d35
Absolute, XADC $aaaa,X$7d35
Absolute, YADC $aaaa,Y$7935
IndirectADC ($zz)$7237
Indexed IndirectADC ($zz,X)$6127
Indirect, IndexADC ($zz),Y$7127

AND - AND Accumulator with Memory

NVTDIZC
? 0  ? 
Addressing ModeSyntaxOpcodeBytesCycles
ImmediateAND #$ii$2922
Zero PageAND $zz$2524
Zero Page, XAND $zz,X$3524
AbsoluteAND $aaaa$2d35
Absolute, XAND $aaaa,X$3d35
Absolute, YAND $aaaa,Y$3935
IndirectAND ($zz)$3237
Indexed IndirectAND ($zz,X)$2127
Indirect, IndexAND ($zz),Y$3127


ASL - Arithmetic Shift Left

NVTDIZC
? 0  ??

Shifts the value at the location specified by the operand left by one bit, shifting in 0 to Bit0, and writes the result back to that location. Bit7 of the value before the shift is copied to the Carry flag.

Addressing ModeSyntaxOpcodeBytesCycles
AccumulatorASL A$0a12
Zero PageASL $zz$0626
Zero Page, XASL $zz,X$1626
AbsoluteASL $aaaa$0e37
Absolute, XASL $aaaa,X$1e37

BBRn - Branch on Bit Reset n

NVTDIZC
  0    

If Bit 'n' of the value at the effective address specified by the second operand is clear, branch to the address calculated from the second operand. The second operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing ModeSyntaxOpcodeBytesCycles
Zero Page, RelativeBBR0 $zz, $rrrr$0f36*
Zero Page, RelativeBBR1 $zz, $rrrr$1f36*
Zero Page, RelativeBBR2 $zz, $rrrr$2f36*
Zero Page, RelativeBBR3 $zz, $rrrr$3f36*
Zero Page, RelativeBBR4 $zz, $rrrr$4f36*
Zero Page, RelativeBBR5 $zz, $rrrr$5f36*
Zero Page, RelativeBBR6 $zz, $rrrr$6f36*
Zero Page, RelativeBBR7 $zz, $rrrr$7f36*
* Add 2 extra cycles if branch is taken.

BBSn - Branch on Bit Set n

NVTDIZC
  0    

If Bit 'n' of the value at the effective address specified by the operand is set, branch to the address calculated from the second operand. The second operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed second operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing ModeSyntaxOpcodeBytesCycles
Zero Page, RelativeBBS0 $zz, $rrrr$8f36*
Zero Page, RelativeBBS1 $zz, $rrrr$9f36*
Zero Page, RelativeBBS2 $zz, $rrrr$af36*
Zero Page, RelativeBBS3 $zz, $rrrr$bf36*
Zero Page, RelativeBBS4 $zz, $rrrr$cf36*
Zero Page, RelativeBBS5 $zz, $rrrr$df36*
Zero Page, RelativeBBS6 $zz, $rrrr$ef36*
Zero Page, RelativeBBS7 $zz, $rrrr$ff36*
* Add 2 extra cycles if branch is taken.

BCC - Branch on Carry Clear

NVTDIZC
  0    

If the carry flag is clear, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing ModeSyntaxOpcodeBytesCycles
RelativeBCC $rrrr$9022(4 if branch taken)

BCS - Branch on Carry Set

NVTDIZC
  0    

If the carry flag is set, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).


Addressing ModeSyntaxOpcodeBytesCycles
RelativeBCS $rrrr$b022(4 if branch taken)

BEQ - Branch on Equal(Zero Set)

NVTDIZC
  0    

If the zero flag is set, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).


Addressing ModeSyntaxOpcodeBytesCycles
RelativeBEQ $rrrr$f022(4 if branch taken)

BIT - Test Memory Bits with Accumulator

NVTDIZC
??0  ? 
Addressing ModeSyntaxOpcodeBytesCycles
ImmediateBIT #$ii$8922
Zero PageBIT $zz$2424
Zero Page, XBIT $zz,X$3424
AbsoluteBIT $aaaa$2c35
Absolute, XBIT $aaaa,X$3c35

BMI - Branch on Minus(Negative Set)

NVTDIZC
  0    

If the negative flag is set, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).


Addressing ModeSyntaxOpcodeBytesCycles
RelativeBMI $rrrr$3022(4 if branch taken)

BNE - Branch on Not Equal(Zero Clear)

NVTDIZC
  0    

If the zero flag is clear, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).


Addressing ModeSyntaxOpcodeBytesCycles
RelativeBNE $rrrr$d022(4 if branch taken)

BPL - Branch on Plus(Negative Clear)

NVTDIZC
  0    

If the negative flag is clear, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).


Addressing ModeSyntaxOpcodeBytesCycles
RelativeBPL $rrrr$1022(4 if branch taken)

BRA - Branch

NVTDIZC
  0    

Unconditionally branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).


Addressing ModeSyntaxOpcodeBytesCycles
RelativeBRA $rrrr$8024

BRK - Break

NVTDIZC
  001  

Forces a software interrupt using IRQ2's vector. Contrary to IRQs, BRK will push the status flags register with bit 4('B' flag) set.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedBRK$0018

BSR - Branch to Subroutine

NVTDIZC
  0    
Addressing ModeSyntaxOpcodeBytesCycles
RelativeBSR $rrrr$4428

BVC - Branch on Overflow Clear

NVTDIZC
  0    

If the overflow flag is clear, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing ModeSyntaxOpcodeBytesCycles
RelativeBVC $rrrr$5022

BVS - Branch on Overflow Set

NVTDIZC
  0    

If the overflow flag is set, branch to the address calculated from the operand. The operand is treated as an 8-bit signed number, -128 to 127. When calculating the branch address, the 8-bit signed operand is added to the address of the byte immediately following the branch instruction. For example, a branch instruction with an operand of $00 will never branch.

256-byte and 8192-byte page-boundary crossing do not incur cycle penalties, unlike other 6502-based processors(or, depending on how the HuC6280 is engineered internally, ALL branches occur a 1-cycle page-crossing penalty on the HuC6280, regardless of page crossing or not).

Addressing ModeSyntaxOpcodeBytesCycles
RelativeBVS $rrrr$7022

CLA - Clear Accumulator

NVTDIZC
  0    

Clears the accumulator(reset to 0).

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedCLA$6212

CLC - Clear Carry Flag

NVTDIZC
  0   0

Clears the carry flag.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedCLC$1812

CLD - Clear Decimal Flag

NVTDIZC
  00   

Clears the decimal flag, disabling decimal mode.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedCLD$d812

CLI - Clear Interrupt Flag

NVTDIZC
  0 0  

Clears the interrupt flag, allowing IRQs to be processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedCLI$5812

CLV - Clear Overflow Flag

NVTDIZC
 00    
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedCLV$b812

CLX - Clear X

NVTDIZC
  0    
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedCLX$8212

CLY - Clear Y

NVTDIZC
  0    
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedCLY$c212

CMP - Compare Accumulator with Memory

NVTDIZC
? 0  ??
Addressing ModeSyntaxOpcodeBytesCycles
ImmediateCMP #$ii$c922
Zero PageCMP $zz$c524
Zero Page, XCMP $zz,X$d524
AbsoluteCMP $aaaa$cd35
Absolute, XCMP $aaaa,X$dd35
Absolute, YCMP $aaaa,Y$d935
IndirectCMP ($zz)$d237
Indexed IndirectCMP ($zz,X)$c127
Indirect, IndexCMP ($zz),Y$d127

CPX - Compare X with Memory

NVTDIZC
? 0  ??
Addressing ModeSyntaxOpcodeBytesCycles
ImmediateCPX #$ii$e022
Zero PageCPX $zz$e424
AbsoluteCPX $aaaa$ec35

CPY - Compare Y with Memory

NVTDIZC
? 0  ??
Addressing ModeSyntaxOpcodeBytesCycles
ImmediateCPY #$ii$c022
Zero PageCPY $zz$c424
AbsoluteCPY $aaaa$cc35

CSH - Change Speed High

NVTDIZC
  0    
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedCSH$d413

CSL - Change Speed Low

NVTDIZC
  0    
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedCSL$5413

DEC - Decrement

NVTDIZC
? 0  ? 
Addressing ModeSyntaxOpcodeBytesCycles
Zero PageDEC $zz$c626
Zero Page, XDEC $zz,X$d626
AbsoluteDEC $aaaa$ce37
Absolute, XDEC $aaaa,X$de37

DEX - Decrement X

NVTDIZC
? 0  ? 
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedDEX$ca12

DEY - Decrement Y

NVTDIZC
? 0  ? 
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedDEY$8812

EOR - Exclusive OR Accumulator with Memory

NVTDIZC
? 0  ? 

Logically XOR the value referenced by the operand to the accumulator.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateEOR #$ii$4922
Zero PageEOR $zz$4524
Zero Page, XEOR $zz,X$5524
AbsoluteEOR $aaaa$4d35
Absolute, XEOR $aaaa,X$5d35
Absolute, YEOR $aaaa,Y$5935
IndirectEOR ($zz)$5237
Indexed IndirectEOR ($zz,X)$4127
Indirect, IndexEOR ($zz),Y$5127

INC - Increment

NVTDIZC
? 0  ? 

Increments the value of the location specified by the operand by one. The Carry flag is not used, nor is it modified.

Addressing ModeSyntaxOpcodeBytesCycles
AccumulatorINC A$1a12
Zero PageINC $zz$e626
Zero Page, XINC $zz,X$f626
AbsoluteINC $aaaa$ee37
Absolute, XINC $aaaa,X$fe37

INX - Increment X

NVTDIZC
? 0  ? 

Increments the value in the X register by one. The Carry flag is not used, nor is it modified.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedINX$e812

INY - Increment Y

NVTDIZC
? 0  ? 

Increments the value in the Y register by one. The Carry flag is not used, nor is it modified.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedINY$c812

JMP - Jump

NVTDIZC
  0    

Transfers control(sets the program counter) to the effective address calculated from the operand.

Addressing ModeSyntaxOpcodeBytesCycles
AbsoluteJMP $aaaa$4c34
IndirectJMP ($aaaa)$6c37
Indexed IndirectJMP ($aaaa,X)$7c37

JSR - Jump to Subroutine

NVTDIZC
  0    
Addressing ModeSyntaxOpcodeBytesCycles
AbsoluteJSR $aaaa$2037

LDA - Load Accumulator

NVTDIZC
? 0  ? 

Loads the accumulator with the value at the effective address.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateLDA #$ii$a922
Zero PageLDA $zz$a524
Zero Page, XLDA $zz,X$b524
AbsoluteLDA $aaaa$ad35
Absolute, XLDA $aaaa,X$bd35
Absolute, YLDA $aaaa,Y$b935
IndirectLDA ($zz)$b237
Indexed IndirectLDA ($zz,X)$a127
Indirect, IndexLDA ($zz),Y$b127

LDX - Load X

NVTDIZC
? 0  ? 

Loads the X register with the value at the effective address.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateLDX #$ii$a222
Zero PageLDX $zz$a624
Zero Page, YLDX $zz,Y$b624
AbsoluteLDX $aaaa$ae35
Absolute, YLDX $aaaa,Y$be35

LDY - Load Y

NVTDIZC
? 0  ? 

Loads the Y register with the value at the effective address.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateLDY #$ii$a022
Zero PageLDY $zz$a424
Zero Page, XLDY $zz,X$b424
AbsoluteLDY $aaaa$ac35
Absolute, XLDY $aaaa,X$bc35

LSR - Logical Shift Right

NVTDIZC
? 0  ?0
Addressing ModeSyntaxOpcodeBytesCycles
AccumulatorLSR A$4a12
Zero PageLSR $zz$4626
Zero Page, XLSR $zz,X$5626
AbsoluteLSR $aaaa$4e37
Absolute, XLSR $aaaa,X$5e37

NOP - No Operation

NVTDIZC
  0    
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedNOP$ea12

ORA - OR Accumulator with Memory

NVTDIZC
? 0  ? 

Logically OR the value referenced by the operand with the accumulator, storing the result in the accumulator.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateORA #$ii$0922
Zero PageORA $zz$0524
Zero Page, XORA $zz,X$1524
AbsoluteORA $aaaa$0d35
Absolute, XORA $aaaa,X$1d35
Absolute, YORA $aaaa,Y$1935
IndirectORA ($zz)$1237
Indexed IndirectORA ($zz,X)$0127
Indirect, IndexORA ($zz),Y$1127

PHA - Push A

NVTDIZC
  0    

Pushes the accumulator to the stack.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedPHA$4813

PHP - Push P

NVTDIZC
  0    

Pushes the status flags(1 byte) to the stack.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedPHP$0813

PHX - Push X

NVTDIZC
  0    

Pushes the X register to the stack.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedPHX$da13

PHY - Push Y

NVTDIZC
  0    

Pushes the Y register to the stack.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedPHY$5a13

PLA - Pull A

NVTDIZC
? 0  ? 

Pulls a value off the stack, and stores the value in the accumulator.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedPLA$6814

PLP - Pull P

NVTDIZC
???????
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedPLP$2814


PLX - Pull X

NVTDIZC
? 0  ? 

Pulls a value off the stack, and stores the value in the X register.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedPLX$fa14

PLY - Pull Y

NVTDIZC
? 0  ? 

Pulls a value off the stack, and stores the value in Y register.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedPLY$7a14

RMBn - Reset Memory Bit n

NVTDIZC
  0    

Reads the zero-page address specified by the operand, resets(clears) the bit "n", and then writes it back to the aforementioned address.

Addressing ModeSyntaxOpcodeBytesCycles
Zero PageRMB0 $zz$0727
Zero PageRMB1 $zz$1727
Zero PageRMB2 $zz$2727
Zero PageRMB3 $zz$3727
Zero PageRMB4 $zz$4727
Zero PageRMB5 $zz$5727
Zero PageRMB6 $zz$6727
Zero PageRMB7 $zz$7727

ROL - Rotate Left

NVTDIZC
? 0  ??
Addressing ModeSyntaxOpcodeBytesCycles
AccumulatorROL A$2a12
Zero PageROL $zz$2626
Zero Page, XROL $zz,X$3626
AbsoluteROL $aaaa$2e37
Absolute, XROL $aaaa,X$3e37

ROR - Rotate Right

NVTDIZC
? 0  ??
Addressing ModeSyntaxOpcodeBytesCycles
AccumulatorROR A$6a12
Zero PageROR $zz$6626
Zero Page, XROR $zz,X$7626
AbsoluteROR $aaaa$6e37
Absolute, XROR $aaaa,X$7e37

RTI - Return from Interrupt

NVTDIZC
???????
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedRTI$4017


RTS - Return from Subroutine

NVTDIZC
  0    
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedRTS$6017


SAX - Swap A and X

NVTDIZC
  0    

Swaps the values in the accumulator and X register.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedSAX$2213

SAY - Swap A and Y

NVTDIZC
  0    

Swap the values in the accumulator and Y register.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedSAY$4213

SBC - Subtract with Borrow

NVTDIZC
??0  ??

If the Decimal-mode CPU flag is set, an extra cycle will be taken(*confirmed with Immediate mode only, however, other addressing modes need to be tested, but should yield the same result).

The overflow flag is not affected by this instruction if in Decimal mode.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateSBC #$ii$e922
Zero PageSBC $zz$e524
Zero Page, XSBC $zz,X$f524
AbsoluteSBC $aaaa$ed35
Absolute, XSBC $aaaa,X$fd35
Absolute, YSBC $aaaa,Y$f935
IndirectSBC ($zz)$f237
Indexed IndirectSBC ($zz,X)$e127
Indirect, IndexSBC ($zz),Y$f127

SEC - Set Carry Flag

NVTDIZC
  0   1

Sets the carry flag.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedSEC$3812

SED - Set Decimal Flag

NVTDIZC
  01   

Sets the decimal flag, enabling decimal mode.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedSED$f812

SEI - Set Interrupt Flag

NVTDIZC
  0 1  

Sets the interrupt flag, preventing IRQs from being processed(note that a change in the interrupt flag with SEI/CLI will only prevent/allow interrupts AFTER the next instruction is executed).

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedSEI$7812

SET - Set T Flag

NVTDIZC
  1    

Sets the T flag, which changes the behavior of the next instruction if the next instruction is ADC, AND, EOR, ORA, or SBC, in which case the operation is performed on the zero-page address specified by the X register, instead of the accumulator.

Note that interrupt processing preserves the T-flag, and clears the T-flag in the interrupt handler, so a programmer needn't worry about an interrupt occuring between SET and the next instruction.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedSET$f412

SMBn - Set Memory Bit n

NVTDIZC
  0    

Reads the zero-page address specified by the operand, sets the bit "n", and then writes it back to the aforementioned address.

Addressing ModeSyntaxOpcodeBytesCycles
Zero PageSMB0 $zz$8727
Zero PageSMB1 $zz$9727
Zero PageSMB2 $zz$a727
Zero PageSMB3 $zz$b727
Zero PageSMB4 $zz$c727
Zero PageSMB5 $zz$d727
Zero PageSMB6 $zz$e727
Zero PageSMB7 $zz$f727

ST0 - Store (HuC6270) VDC No. 0

NVTDIZC
  0    

Writes the immediate value to the physical address $1FE000, the (HuC6270) VDC's address register.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateST0 #$ii$0325

ST1 - Store (HuC6270) VDC No. 1

NVTDIZC
  0    

Writes the immediate value to the physical address $1FE002, the (HuC6270) VDC's lower data register.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateST1 #$ii$1325

ST2 - Store (HuC6270) VDC No. 2

NVTDIZC
  0    

Writes the immediate value to the physical address $1FE003, the (HuC6270) VDC's upper data register.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateST2 #$ii$2325

STA - Store Accumulator

NVTDIZC
  0    

Stores the value in the accumulator to the effective address specified by the operand.

Addressing ModeSyntaxOpcodeBytesCycles
Zero PageSTA $zz$8524
Zero Page, XSTA $zz,X$9524
AbsoluteSTA $aaaa$8d35
Absolute, XSTA $aaaa,X$9d35
Absolute, YSTA $aaaa,Y$9935
IndirectSTA ($zz)$9237
Indexed IndirectSTA ($zz,X)$8127
Indirect, IndexSTA ($zz),Y$9127

STX - Store X

NVTDIZC
  0    

Stores the value in the X register to the effective address specified by the operand.

Addressing ModeSyntaxOpcodeBytesCycles
Zero PageSTX $zz$8624
Zero Page, YSTX $zz,Y$9624
AbsoluteSTX $aaaa$8e35

STY - Store Y

NVTDIZC
  0    

Stores the value in the Y register to the effective address specified by the operand.

Addressing ModeSyntaxOpcodeBytesCycles
Zero PageSTY $zz$8424
Zero Page, XSTY $zz,X$9424
AbsoluteSTY $aaaa$8c35

STZ - Store Zero

NVTDIZC
  0    

Stores zero to the effective address specified by the operand.

Addressing ModeSyntaxOpcodeBytesCycles
Zero PageSTZ $zz$6424
Zero Page, XSTZ $zz,X$7424
AbsoluteSTZ $aaaa$9c35
Absolute, XSTZ $aaaa,X$9e35

SXY - Swap X and Y

NVTDIZC
  0    

Swaps the values in the X register and the Y register.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedSXY$0213

TAI - Transfer Alternate Increment

NVTDIZC
  0    

Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):

Alternate = 0
Do
 Value = Read(ssss + Alternate)
 Write(dddd, value)
 dddd = dddd + 1
 llll = llll - 1
 Alternate = Alternate ^ 1
While llll != 0

It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0" will be effectively treated as a length of "65536".

Please note that the cycles-per-byte-transferred will be higher if (HuC6270) VDC registers are used as source and/or destination.

All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.

Addressing ModeSyntaxOpcodeBytesCycles
Block TransferTAI $ssss, $dddd, $llll$f3717 + 6 * llll

TAM - Transfer Accumulator to MPRs

NVTDIZC
  0    

Copies the value in the accumulator to each MPR with the corresponding bit set in the immediate operand, eg. TAM #$41 will load MPR0 and MPR6 with the value in the accumulator. If no bits are set, no transfer will occur, and the instruction is effectively a 5-cycle NOP.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateTAM #$ii$5325

TAX - Transfer Accumulator to X

NVTDIZC
? 0  ? 

Copies the value of the accumulator to the X register.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedTAX$aa12

TAY - Transfer Accumulator to Y

NVTDIZC
? 0  ? 

Copies the value of the accumulator to the Y register.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedTAY$a812

TDD - Transfer Decrement Decrement

NVTDIZC
  0    

Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):

Do
 Value = Read(ssss)
 Write(dddd, value)
 ssss = ssss - 1
 dddd = dddd - 1
 llll = llll - 1
While llll != 0

It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0" will be effectively treated as a length of "65536".

Please note that the cycles-per-byte-transferred will be higher if (HuC6270) VDC registers are used as source and/or destination.

All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.

Addressing ModeSyntaxOpcodeBytesCycles
Block TransferTDD $ssss, $dddd, $llll$c3717 + 6 * llll

TIA - Transfer Increment Alternate

NVTDIZC
  0    


Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):

Alternate = 0
Do
 Value = Read(ssss)
 Write(dddd + Alternate, Value)
 ssss = ssss + 1
 llll = llll - 1
 Alternate = Alternate ^ 1
While llll != 0

It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0" will be effectively treated as a length of "65536".

All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.

Please note that the cycles-per-byte-transferred will be higher if (HuC6270) VDC registers are used as source and/or destination.

Addressing ModeSyntaxOpcodeBytesCycles
Block TransferTIA $ssss, $dddd, $llll$e3717 + 6 * llll

TII - Transfer Increment Increment

NVTDIZC
  0    

Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):

Do
 Value = Read(ssss)
 Write(dddd, Value)
 ssss = ssss + 1
 dddd = dddd + 1
 llll = llll - 1
While llll != 0

It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0" will be effectively treated as a length of "65536".

All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.

Please note that the cycles-per-byte-transferred will be higher if (HuC6270) VDC registers are used as source and/or destination.

Addressing ModeSyntaxOpcodeBytesCycles
Block TransferTII $ssss, $dddd, $llll$73717 + 6 * llll

TIN - Transfer Increment

NVTDIZC
  0    

Enters block memory transfer sequence shown by this pseudocode('ssss' is the 16-bit source address, 'dddd' is the 16-bit destination address, and 'llll' is the 16-bit length counter, in bytes):

Do
 Value = Read(ssss)
 Write(dddd, value)
 ssss = ssss + 1
 llll = llll - 1
While llll != 0

It is important to note that the comparison of the length counter to 0 is done AFTER the length counter is decremented, not before, so a length of "0" will be effectively treated as a length of "65536".

All block-transfer instructions push Y, A, X in that order before beginning the block transfer, and pop X, A, Y in that order after the transfer is complete.

Please note that the cycles-per-byte-transferred will be higher if (HuC6270) VDC registers are used as source and/or destination.

Addressing ModeSyntaxOpcodeBytesCycles
Block TransferTIN $ssss, $dddd, $llll$d3717 + 6 * llll

TMA - Transfer MPR to Accumulator

NVTDIZC
  0    

Copies the value in the MPR, specified by the corresponding bit being set in the immediate operand, to the accumulator. If an immediate value of $00 is used, the accumulator will be loaded with the last value transfered by TAM(note that if an immediate value of $00 is used with TAM, no transfer occurs, and as such won't be read back if an immediate value of $00 is used with TMA). Undefined behavior results if multiple bits are set.

Addressing ModeSyntaxOpcodeBytesCycles
ImmediateTMA #$ii$4324

TRB - Test and Reset Bits against Accumulator

NVTDIZC
??0  ? 

Loads the value specified by the effective address of the operand, clears all bits whose corresponding bits are set in the accumulator(result = value & ~accumulator), and stores the result to the aforementioned address.

The zero flag is set according to the result. The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address, before it is operated on.

Addressing ModeSyntaxOpcodeBytesCycles
Zero PageTRB $zz$1426
AbsoluteTRB $aaaa$1c37

TSB - Test and Set Bits against Accumulator

NVTDIZC
??0  ? 

Loads the value specified by the effective address of the operand, sets all bits whose corresponding bits are set in the accumulator(result = value & ~accumulator), and stores the result to the aforementioned address.

The zero flag is set according to the result. The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address, before it is operated on.

Addressing ModeSyntaxOpcodeBytesCycles
Zero PageTSB $zz$0426
AbsoluteTSB $aaaa$0c37

TST - Test

NVTDIZC
??0  ? 

The N and V flags are copied from bit7 and bit6 of the value loaded from the effective address(they are *not* set as the result of the AND operation used to determine the Z flag's state).

The Z flag is determined according to the result of logically AND'ing the immediate value and the value at the effective address.

Addressing ModeSyntaxOpcodeBytesCycles
Immediate, Zero PageTST #$ii, $zz$8337
Immediate, Zero Page, XTST #$ii, $zz, X$a337
Immediate, AbsoluteTST #$ii, $aaaa$9348
Immediate, Absolute, XTST #$ii, $aaaa, X$b348

TSX - Transfer Stack Pointer to X

NVTDIZC
? 0  ? 
Addressing ModeSyntaxOpcodeBytesCycles
ImpliedTSX$ba12

TXA - Transfer X to A

NVTDIZC
? 0  ? 

Copies the value in the X register to the Accumulator.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedTXA$8a12

TXS - Track X to Stack Pointer

NVTDIZC
  0    

Copies the value in X to the stack pointer.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedTXS$9a12

TYA - Transfer Y to Accumulator

NVTDIZC
? 0  ? 

Copies the value in Y to the Accumulator.

Addressing ModeSyntaxOpcodeBytesCycles
ImpliedTYA$9812