Difference between revisions of "MSM5205"
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| − | overview | + | == overview == |
the adpcm playback hardware consists of the following components | the adpcm playback hardware consists of the following components | ||
asic nec gate array containing adpcm control logic oki msm5205 adpcm decoder 1 channel two m41464 drams 64Kx4 for sample storage | asic nec gate array containing adpcm control logic oki msm5205 adpcm decoder 1 channel two m41464 drams 64Kx4 for sample storage | ||
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----v---- s1 01 18 | ----v---- s1 01 18 | ||
| − | vdd s2 02 17 xt 4b 3b 03 16 xt d0 04 15 reset d1 05 14 vck d2 06 13 t2 d3 07 12 t1 n c 08 11 n c vss 09 10 daout --------- s1 sample rate select input 1 2 s2 sample rate select input 2 2 4b 3b adpcm data size 0 3-bit samples; set d0 gnd 1 4-bit samples d3-d0 adpcm data input xt xt clock input typically a 384 khz ceramic resonator if using an external oscillator connect it to xt and leave xt unconnected vck output strobe that is triggered at the sample rate used to latch d0-d3 reset hold high for at least two vck pulses to reset the chip t1 t2 test mode pins set t1 gnd t2 n c daout analog output from internal dac 5vp-p vdd 5v sample rate selection s1 s2 0 0 xt 96 0 1 xt 64 1 0 xt 48 1 1 not documented for a 384 khz clock source these are 4 6 and 8 khz respectively msm5205 configuration msm5205 configuration msm5205 configuration 4b 3b tied to 5v 4-bit sample format selected s1 tied to 5v s2 tied to gnd internal clock divider set to 48 test mode pins are not used asic drives xt reset and inputs vck xt is not used dram configuration dram configuration dram configuration the cpu interface to adpcm ram looks like a 64kx8 array however to the chip it is a 128kx4 array and samples can start on any nibble boundary the sample length is always specified in byte two-sample units msm5205 timing | + | vdd s2 02 17 xt 4b 3b 03 16 xt d0 04 15 reset d1 05 14 vck d2 06 13 t2 d3 07 12 t1 n c 08 11 n c vss 09 10 daout --------- s1 sample rate select input 1 2 s2 sample rate select input 2 2 4b 3b adpcm data size 0 3-bit samples; set d0 gnd 1 4-bit samples d3-d0 adpcm data input xt xt clock input typically a 384 khz ceramic resonator if using an external oscillator connect it to xt and leave xt unconnected vck output strobe that is triggered at the sample rate used to latch d0-d3 reset hold high for at least two vck pulses to reset the chip t1 t2 test mode pins set t1 gnd t2 n c daout analog output from internal dac 5vp-p vdd 5v sample rate selection s1 s2 0 0 xt 96 0 1 xt 64 1 0 xt 48 1 1 not documented for a 384 khz clock source these are 4 6 and 8 khz respectively msm5205 configuration msm5205 configuration msm5205 configuration 4b 3b tied to 5v 4-bit sample format selected s1 tied to 5v s2 tied to gnd internal clock divider set to 48 test mode pins are not used asic drives xt reset and inputs vck xt is not used dram configuration dram configuration dram configuration the cpu interface to adpcm ram looks like a 64kx8 array however to the chip it is a 128kx4 array and samples can start on any nibble boundary the sample length is always specified in byte two-sample units |
| + | |||
| + | == msm5205 timing == | ||
| + | |||
| + | typically the msm5205 is used with a 384 khz resonator and a divider of 48 provides an effective sample rate of exactly 8 000 hz however the pce implementation provides a programmable clock effectively over- or underclocking the chip to allow more sample rates to be selected the asic divides a 1 540 200 mhz clock to provide the clock signal fed to the msm5205 xt pin the divider is set by writing to the lower 4 bits of 180e | ||
| + | |||
| + | 180e divider xt frequency sample rate xt | ||
| + | 48 00 16 96 270 hz | ||
| + | 2 005 46875 hz | ||
| + | 01 15 102 680hz | ||
| + | 2 139 166667 hz | ||
| + | 02 14 110 020 hz | ||
| + | 2 292 083333 hz | ||
| + | 03 13 118 480 hz | ||
| + | 2 468 333333 hz | ||
| + | 04 12 128 350 hz | ||
| + | 2 673 958333 hz | ||
| + | 05 11 140 020 hz | ||
| + | 2 917 083333 hz | ||
| + | 06 10 154 020 hz | ||
| + | 3 208 75 hz | ||
| + | 07 9 171 140 hz | ||
| + | 3 565 416667 hz | ||
| + | 08 8 192 530 hz | ||
| + | 4 010 8375 hz | ||
| + | 09 7 220 030 hz | ||
| + | 4 583 958333 hz | ||
| + | 0a 6 256 700 hz | ||
| + | 5 347 916667 hz | ||
| + | 0b 5 308 050 hz | ||
| + | 6 417 708333 hz | ||
| + | 0c 4 385 050 hz | ||
| + | 8 021 875 hz | ||
| + | 0d 3 513 400 hz | ||
| + | 10 695 8 hz | ||
| + | 0e 2 770 100 hz | ||
| + | 16 043 75 hz | ||
| + | 0f 1 1 540 200 hz | ||
| + | 32 087 5 hz | ||
| + | |||
| + | to determine how much playback time you get for each sample rate divide the total number of samples that can be contained in ram 131 072 samples by the sample rate to get the playback time in seconds note according to the turboduo schematics there is a 9 21 mhz ceramic resonator connected to the asic assuming it is divided by 6 before being adjusted by 180e that gives the base frequency of 1 535 mhz for adpcm decoding my measurements were at the xt pin and seem to be close enough adpcm format adpcm format adpcm format the oki adpcm format is identical to the intel dialogic vox format the \'sound exchange\' utility \'sox\' supports this format and the non-standard sample rates the pce uses the vox format has no header or other information to specify the sample rate so that must be explictly stated during conversion some examples are as follows ; convert 8 khz adpcm data to wav file sox -r 8000 test vox test wav ; convert wav file to 32 khz adpcm data sox music wav -r 32000 music vox the resulting headerloss vox file can be directly included into a program as binary data and stored to adpcm ram for playback links links links sound exchange category pc engine | ||
Revision as of 06:59, 10 November 2010
PAGE RECOVERY
overview
the adpcm playback hardware consists of the following components asic nec gate array containing adpcm control logic oki msm5205 adpcm decoder 1 channel two m41464 drams 64Kx4 for sample storage
msm5205 pin assignments
comes in an 18-pin plastic dip with oki m5205 stamped on it
v---- s1 01 18
vdd s2 02 17 xt 4b 3b 03 16 xt d0 04 15 reset d1 05 14 vck d2 06 13 t2 d3 07 12 t1 n c 08 11 n c vss 09 10 daout --------- s1 sample rate select input 1 2 s2 sample rate select input 2 2 4b 3b adpcm data size 0 3-bit samples; set d0 gnd 1 4-bit samples d3-d0 adpcm data input xt xt clock input typically a 384 khz ceramic resonator if using an external oscillator connect it to xt and leave xt unconnected vck output strobe that is triggered at the sample rate used to latch d0-d3 reset hold high for at least two vck pulses to reset the chip t1 t2 test mode pins set t1 gnd t2 n c daout analog output from internal dac 5vp-p vdd 5v sample rate selection s1 s2 0 0 xt 96 0 1 xt 64 1 0 xt 48 1 1 not documented for a 384 khz clock source these are 4 6 and 8 khz respectively msm5205 configuration msm5205 configuration msm5205 configuration 4b 3b tied to 5v 4-bit sample format selected s1 tied to 5v s2 tied to gnd internal clock divider set to 48 test mode pins are not used asic drives xt reset and inputs vck xt is not used dram configuration dram configuration dram configuration the cpu interface to adpcm ram looks like a 64kx8 array however to the chip it is a 128kx4 array and samples can start on any nibble boundary the sample length is always specified in byte two-sample units
msm5205 timing
typically the msm5205 is used with a 384 khz resonator and a divider of 48 provides an effective sample rate of exactly 8 000 hz however the pce implementation provides a programmable clock effectively over- or underclocking the chip to allow more sample rates to be selected the asic divides a 1 540 200 mhz clock to provide the clock signal fed to the msm5205 xt pin the divider is set by writing to the lower 4 bits of 180e
180e divider xt frequency sample rate xt 48 00 16 96 270 hz 2 005 46875 hz 01 15 102 680hz 2 139 166667 hz 02 14 110 020 hz 2 292 083333 hz 03 13 118 480 hz 2 468 333333 hz 04 12 128 350 hz 2 673 958333 hz 05 11 140 020 hz 2 917 083333 hz 06 10 154 020 hz 3 208 75 hz 07 9 171 140 hz 3 565 416667 hz 08 8 192 530 hz 4 010 8375 hz 09 7 220 030 hz 4 583 958333 hz 0a 6 256 700 hz 5 347 916667 hz 0b 5 308 050 hz 6 417 708333 hz 0c 4 385 050 hz 8 021 875 hz 0d 3 513 400 hz 10 695 8 hz 0e 2 770 100 hz 16 043 75 hz 0f 1 1 540 200 hz 32 087 5 hz
to determine how much playback time you get for each sample rate divide the total number of samples that can be contained in ram 131 072 samples by the sample rate to get the playback time in seconds note according to the turboduo schematics there is a 9 21 mhz ceramic resonator connected to the asic assuming it is divided by 6 before being adjusted by 180e that gives the base frequency of 1 535 mhz for adpcm decoding my measurements were at the xt pin and seem to be close enough adpcm format adpcm format adpcm format the oki adpcm format is identical to the intel dialogic vox format the \'sound exchange\' utility \'sox\' supports this format and the non-standard sample rates the pce uses the vox format has no header or other information to specify the sample rate so that must be explictly stated during conversion some examples are as follows ; convert 8 khz adpcm data to wav file sox -r 8000 test vox test wav ; convert wav file to 32 khz adpcm data sox music wav -r 32000 music vox the resulting headerloss vox file can be directly included into a program as binary data and stored to adpcm ram for playback links links links sound exchange category pc engine
