Difference between revisions of "Memory Map"

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The 2MB physical address space available to the HuC6280 contains all of the memory-mapped I/O necessary to interface with the other chips, the CD subsystem, and the user (through the HuCard and joystick ports). Below is the full memory map for the TurboGrafx / PC Engine family. Each segment is labeled with its corresponding MPR register value ($00 - $FF), a description of the segment's use, its physical address location, and a "chip enable signal" or other descriptive text. The Develo Book describes the chip enable signal as an external signal that becomes true when that area of memory is accessed. Currently, it is not known if these signals correspond with any pins or traces available on the system motherboard. Signals in parentheses, such as ([o]CEP[/o]), represent chip enable signals that are internal to the HuC6280. The notation [o]SIGNAME[/o] is equivalent to a negative logic signal; that is, the signal is active when it is low instead of high.
 
The 2MB physical address space available to the HuC6280 contains all of the memory-mapped I/O necessary to interface with the other chips, the CD subsystem, and the user (through the HuCard and joystick ports). Below is the full memory map for the TurboGrafx / PC Engine family. Each segment is labeled with its corresponding MPR register value ($00 - $FF), a description of the segment's use, its physical address location, and a "chip enable signal" or other descriptive text. The Develo Book describes the chip enable signal as an external signal that becomes true when that area of memory is accessed. Currently, it is not known if these signals correspond with any pins or traces available on the system motherboard. Signals in parentheses, such as ([o]CEP[/o]), represent chip enable signals that are internal to the HuC6280. The notation [o]SIGNAME[/o] is equivalent to a negative logic signal; that is, the signal is active when it is low instead of high.
  
 
== Independent Memory Maps ==
 
== Independent Memory Maps ==
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=== Standard hardware (PC-Engine, CoreGrafx, CoreGrafx II, TurboGrafx 16) ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 1FF400 - 1FF7FF || FF:1400 - FF:17FF || Interrupt controller || [o]CECG[/o] (internal)
 +
|-
 +
| 1FF000 - 1FF3FF || FF:1000 - FF:13FF || 8-bit I/O port || [o]CEIO[/o] (internal)
 +
|-
 +
| 1FE800 - 1FEBFF || FF:0800 - FF:0BFF || PSG registers || [o]CEP[/o] (internal)
 +
|-
 +
| 1FE400 - 1FE7FF || FF:0400 - FF:07FF || VCE registers || [o]CEK[/o]
 +
|-
 +
| 1FE000 - 1FE3FF || FF:0000 - FF:03FF || VDC registers || [o]CE7[/o] (HuC6280 pin 60)
 +
|-
 +
| 1F0000 - 1F7FFF || F8:0000 - FB:1FFF || Work RAM (8K, mirrored four times) || [o]CER[/o] (HuC6280 pin 61)
 +
|-
 +
| 000000 - 0FFFFF || 00:0000 - 7F:1FFF || HuCard/TurboChip ROM || ROM [o]CE[/o] (A20)
 +
|}
 +
 +
 +
 +
=== SuperGrafx additions ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 1FE020 - 1FE3FF || FF:0020 - FF:03FF || Copy of 32-byte register block (mirrored repeatedly) || [o]CE7[/o] (HuC6280 pin 60)
 +
|-
 +
| 1FE018 - 1FE01F || FF:0018 - FF:001F || (Unused) || [o]CE7[/o] (HuC6280 pin 60)
 +
|-
 +
| 1FE010 - 1FE017 || FF:0010 - FF:0017 || VDC #2 registers || [o]CE7[/o] (HuC6280 pin 60)
 +
|-
 +
| 1FE008 - 1FE00F || FF:0008 - FF:000F || VPC registers || [o]CE7[/o] (HuC6280 pin 60)
 +
|-
 +
| 1FE000 - 1FE007 || FF:0000 - FF:0007 || VDC #1 registers || [o]CE7[/o] (HuC6280 pin 60)
 +
|-
 +
| 1F0000 - 1F7FFF || F8:0000 - FB:1FFF || Work RAM (32K) || [o]CER[/o] (HuC6280 pin 61)
 +
|}
 +
 +
 +
 +
=== IFU-30 additions ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 1FE800 - 1FF80F || FF:0800 - FF:180F || CD-ROM / ASIC registers || [o]CEP[/o] (internal)
 +
|-
 +
| 1EE000 - 1EE7FF || F7:0000 - F7:07FF || Back-up RAM (2K) || [o]CER[/o] (HuC6280 pin 61)
 +
|-
 +
| 100000 - 10FFFF || 80:0000 - 87:1FFF || Work RAM (64K) || [o]CER[/o] (HuC6280 pin 61)
 +
|}
 +
 +
 +
 +
=== TurboBooster+ additions ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 1FE800 - 1FF80F || FF:0800 - FF:180F || ASIC registers (only relating to back-up RAM control) || [o]CEP[/o] (internal)
 +
|-
 +
| 1EE000 - 1EE7FF || F7:0000 - F7:07FF || Back-up RAM (2K) || [o]CER[/o] (HuC6280 pin 61)
 +
|}
 +
 +
 +
 +
=== Super CD-ROM2 additions ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 1FE800 - 1FFBFF || FF:0800 - FF:1BFF || CD-ROM / ASIC registers || [o]CEP[/o] (internal)
 +
|-
 +
| 1EE000 - 1EE7FF || F7:0000 - F7:07FF || Back-up RAM (2K) || [o]CER[/o] (HuC6280 pin 61)
 +
|-
 +
| 100000 - 10FFFF || 80:0000 - 87:1FFF || Work RAM (64K) || [o]CER[/o] (HuC6280 pin 61)
 +
|-
 +
| 0D0000 - 0FFFFF || 68:0000 - 7F:1FFF || Work RAM (192K) || ROM [o]CE[/o] (A20)
 +
|-
 +
| 000000 - 07FFFF || 00:0000 - 3F:1FFF || BIOS ROM (512K) || ROM [o]CE[/o] (A20)
 +
|}
 +
 +
 +
 +
=== System Card (v1.x, v2.x) additions ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 000000 - 03FFFF || 00:0000 - 1F:1FFF || BIOS ROM (256K) || ROM [o]CE[/o] (A20)
 +
|}
 +
 +
 +
 +
=== System Card (v3.x) additions ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 1FF800 - 1FF9FF || FF:1800 - FF:19FF || ID locations || [o]CECG[/o] (internal)
 +
|-
 +
| 0D0000 - 0FFFFF || 68:0000 - 7F:1FFF || Work RAM (192K) || ROM [o]CE[/o] (A20)
 +
|-
 +
| 000000 - 07FFFF || 00:0000 - 3F:1FFF || BIOS ROM (512K) || ROM [o]CE[/o] (A20)
 +
|}
 +
 +
 +
 +
=== Arcade Card DUO additions ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 1FFA00 - 1FFBFF || FF:1A00 - FF:1BFF || Arcade Card I/O ports || [o]CECG[/o] (internal)
 +
|-
 +
| 1FF800 - 1FF9FF || FF:1800 - FF:19FF || ID locations || [o]CECG[/o] (internal)
 +
|-
 +
| 080000 - 087FFF || 40:0000 - 43:1FFF || Arcade Card I/O pages || ROM [o]CE[/o] (A20)
 +
|}
 +
 +
 +
 +
=== Arcade Card Pro additions ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 1FFA00 - 1FFBFF || FF:1A00 - FF:1BFF || Arcade Card I/O ports || [o]CECG[/o] (internal)
 +
|-
 +
| 1FF800 - 1FF9FF || FF:1800 - FF:19FF || ID locations || [o]CECG[/o] (internal)
 +
|-
 +
| 0D0000 - 0FFFFF || 68:0000 - 7F:1FFF || Work RAM (192K) || ROM [o]CE[/o] (A20)
 +
|-
 +
| 080000 - 087FFF || 40:0000 - 43:1FFF || Arcade Card I/O pages || ROM [o]CE[/o] (A20)
 +
|-
 +
| 000000 - 07FFFF || 00:0000 - 3F:1FFF || BIOS ROM (512K) || ROM [o]CE[/o] (A20)
 +
|}
 +
 +
 +
 +
=== HuCard/TurboChip "split" format ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 080000 - 0FFFFF || 40:0000 - 7F:1FFF || Mask ROM #2 (can be 128K, 256K) || ROM [o]CE[/o] (A20)
 +
|-
 +
| 000000 - 07FFFF || 00:0000 - 3F:1FFF || Mask ROM #1 (can be 128K, 256K) || ROM [o]CE[/o] (A20)
 +
|}
 +
 +
 +
 +
=== HuCard/TurboChip standard format ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 000000 - 0FFFFF || 00:0000 - 7F:1FFF || Mask ROM (can be 128K, 256K, 512K) || ROM [o]CE[/o] (A20)
 +
|}
 +
 +
 +
 +
=== Street Fighter II CE (HuCard) ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| 080000 - 0FFFFF || 40:0000 - 7F:1FFF || ROM bank (512K of 2MB) || ROM [o]CE[/o] (A20)
 +
|-
 +
| 000000 - 07FFFF || 00:0000 - 3F:1FFF || ROM (512K, fixed) || ROM [o]CE[/o] (A20)
 +
|-
 +
| 001FF0 - 001FF3 || 00:1FF0 - 00:1FF3 || Bank select registers (write to 1FFx to map ROM bank #x to to the bank area) || ROM [o]CE[/o] (A20)
 +
|}
 +
 +
 +
 +
=== "ROMRAM" HuCard (Populous, Tennokoe Bank) ===
 +
 +
{| class="styled_table"
 +
! Physical Addresses !! Segment : Address !! Description !! Chip enable signal
 +
|-
 +
| ?????? - ?????? || ??:???? - ??:???? || Battery-backed RAM ||
 +
|-
 +
| 000000 - 0FFFFF || 00:0000 - 7F:1FFF || Game ROM (256K) || ROM [o]CE[/o] (A20)
 +
|}
 +
 +
 +
 +
 +
 +
 +
 +
 +
 +
 +
 +
 +
  
 
===  Standard hardware (PC-Engine, CoreGrafx, CoreGrafx II, TurboGrafx 16) ===
 
===  Standard hardware (PC-Engine, CoreGrafx, CoreGrafx II, TurboGrafx 16) ===

Revision as of 10:51, 20 July 2014


The 2MB physical address space available to the HuC6280 contains all of the memory-mapped I/O necessary to interface with the other chips, the CD subsystem, and the user (through the HuCard and joystick ports). Below is the full memory map for the TurboGrafx / PC Engine family. Each segment is labeled with its corresponding MPR register value ($00 - $FF), a description of the segment's use, its physical address location, and a "chip enable signal" or other descriptive text. The Develo Book describes the chip enable signal as an external signal that becomes true when that area of memory is accessed. Currently, it is not known if these signals correspond with any pins or traces available on the system motherboard. Signals in parentheses, such as (CEP), represent chip enable signals that are internal to the HuC6280. The notation SIGNAME is equivalent to a negative logic signal; that is, the signal is active when it is low instead of high.

Independent Memory Maps


Standard hardware (PC-Engine, CoreGrafx, CoreGrafx II, TurboGrafx 16)

Physical Addresses Segment : Address Description Chip enable signal
1FF400 - 1FF7FF FF:1400 - FF:17FF Interrupt controller CECG (internal)
1FF000 - 1FF3FF FF:1000 - FF:13FF 8-bit I/O port CEIO (internal)
1FE800 - 1FEBFF FF:0800 - FF:0BFF PSG registers CEP (internal)
1FE400 - 1FE7FF FF:0400 - FF:07FF VCE registers CEK
1FE000 - 1FE3FF FF:0000 - FF:03FF VDC registers CE7 (HuC6280 pin 60)
1F0000 - 1F7FFF F8:0000 - FB:1FFF Work RAM (8K, mirrored four times) CER (HuC6280 pin 61)
000000 - 0FFFFF 00:0000 - 7F:1FFF HuCard/TurboChip ROM ROM CE (A20)


SuperGrafx additions

Physical Addresses Segment : Address Description Chip enable signal
1FE020 - 1FE3FF FF:0020 - FF:03FF Copy of 32-byte register block (mirrored repeatedly) CE7 (HuC6280 pin 60)
1FE018 - 1FE01F FF:0018 - FF:001F (Unused) CE7 (HuC6280 pin 60)
1FE010 - 1FE017 FF:0010 - FF:0017 VDC #2 registers CE7 (HuC6280 pin 60)
1FE008 - 1FE00F FF:0008 - FF:000F VPC registers CE7 (HuC6280 pin 60)
1FE000 - 1FE007 FF:0000 - FF:0007 VDC #1 registers CE7 (HuC6280 pin 60)
1F0000 - 1F7FFF F8:0000 - FB:1FFF Work RAM (32K) CER (HuC6280 pin 61)


IFU-30 additions

Physical Addresses Segment : Address Description Chip enable signal
1FE800 - 1FF80F FF:0800 - FF:180F CD-ROM / ASIC registers CEP (internal)
1EE000 - 1EE7FF F7:0000 - F7:07FF Back-up RAM (2K) CER (HuC6280 pin 61)
100000 - 10FFFF 80:0000 - 87:1FFF Work RAM (64K) CER (HuC6280 pin 61)


TurboBooster+ additions

Physical Addresses Segment : Address Description Chip enable signal
1FE800 - 1FF80F FF:0800 - FF:180F ASIC registers (only relating to back-up RAM control) CEP (internal)
1EE000 - 1EE7FF F7:0000 - F7:07FF Back-up RAM (2K) CER (HuC6280 pin 61)


Super CD-ROM2 additions

Physical Addresses Segment : Address Description Chip enable signal
1FE800 - 1FFBFF FF:0800 - FF:1BFF CD-ROM / ASIC registers CEP (internal)
1EE000 - 1EE7FF F7:0000 - F7:07FF Back-up RAM (2K) CER (HuC6280 pin 61)
100000 - 10FFFF 80:0000 - 87:1FFF Work RAM (64K) CER (HuC6280 pin 61)
0D0000 - 0FFFFF 68:0000 - 7F:1FFF Work RAM (192K) ROM CE (A20)
000000 - 07FFFF 00:0000 - 3F:1FFF BIOS ROM (512K) ROM CE (A20)


System Card (v1.x, v2.x) additions

Physical Addresses Segment : Address Description Chip enable signal
000000 - 03FFFF 00:0000 - 1F:1FFF BIOS ROM (256K) ROM CE (A20)


System Card (v3.x) additions

Physical Addresses Segment : Address Description Chip enable signal
1FF800 - 1FF9FF FF:1800 - FF:19FF ID locations CECG (internal)
0D0000 - 0FFFFF 68:0000 - 7F:1FFF Work RAM (192K) ROM CE (A20)
000000 - 07FFFF 00:0000 - 3F:1FFF BIOS ROM (512K) ROM CE (A20)


Arcade Card DUO additions

Physical Addresses Segment : Address Description Chip enable signal
1FFA00 - 1FFBFF FF:1A00 - FF:1BFF Arcade Card I/O ports CECG (internal)
1FF800 - 1FF9FF FF:1800 - FF:19FF ID locations CECG (internal)
080000 - 087FFF 40:0000 - 43:1FFF Arcade Card I/O pages ROM CE (A20)


Arcade Card Pro additions

Physical Addresses Segment : Address Description Chip enable signal
1FFA00 - 1FFBFF FF:1A00 - FF:1BFF Arcade Card I/O ports CECG (internal)
1FF800 - 1FF9FF FF:1800 - FF:19FF ID locations CECG (internal)
0D0000 - 0FFFFF 68:0000 - 7F:1FFF Work RAM (192K) ROM CE (A20)
080000 - 087FFF 40:0000 - 43:1FFF Arcade Card I/O pages ROM CE (A20)
000000 - 07FFFF 00:0000 - 3F:1FFF BIOS ROM (512K) ROM CE (A20)


HuCard/TurboChip "split" format

Physical Addresses Segment : Address Description Chip enable signal
080000 - 0FFFFF 40:0000 - 7F:1FFF Mask ROM #2 (can be 128K, 256K) ROM CE (A20)
000000 - 07FFFF 00:0000 - 3F:1FFF Mask ROM #1 (can be 128K, 256K) ROM CE (A20)


HuCard/TurboChip standard format

Physical Addresses Segment : Address Description Chip enable signal
000000 - 0FFFFF 00:0000 - 7F:1FFF Mask ROM (can be 128K, 256K, 512K) ROM CE (A20)


Street Fighter II CE (HuCard)

Physical Addresses Segment : Address Description Chip enable signal
080000 - 0FFFFF 40:0000 - 7F:1FFF ROM bank (512K of 2MB) ROM CE (A20)
000000 - 07FFFF 00:0000 - 3F:1FFF ROM (512K, fixed) ROM CE (A20)
001FF0 - 001FF3 00:1FF0 - 00:1FF3 Bank select registers (write to 1FFx to map ROM bank #x to to the bank area) ROM CE (A20)


"ROMRAM" HuCard (Populous, Tennokoe Bank)

Physical Addresses Segment : Address Description Chip enable signal
 ?????? - ??????  ??:???? - ??:???? Battery-backed RAM
000000 - 0FFFFF 00:0000 - 7F:1FFF Game ROM (256K) ROM CE (A20)








Standard hardware (PC-Engine, CoreGrafx, CoreGrafx II, TurboGrafx 16)

Physical Addresses Segment # Description Chip enable signal
1FFC00-1FFFFF FF Reserved for expansion
1FF800-1FFBFF FF Reserved for expansion
1FF400-1FF7FF FF Interrupt controller (CECG)
1FF000-1FF3FF FF 8-bit I/O port (CEIO)
1FE800-1FEBFF FF PSG registers (CEP)
1FE400-1FE7FF FF VCE registers CEK
1FE000-1FE3FF FF VDC registers CE7
1F0000-1F7FFF F8-FB Work RAM (8K, mirrored four times) CER
000000-0FFFFF 00-7F HuCard/TurboChip ROM (card-specific) Typically A20 is used as ROM CE


SuperGrafx additions

Physical Addresses Segment # Description
1FE020-1FE3FF FF Copy of 32-byte register block (mirrored repeatedly)
1FE018-1FE01F FF (Unused)
1FE010-1FE017 FF VDC #2 registers
1FE008-1FE00F FF VPC registers
1FE000-1FE007 FF VDC #1 registers
1F0000-1F7FFF F8-FB Work RAM (32K)


IFU-30 additions

Physical Addresses Segment # Description
1FE800-1FF80F FF CD-ROM / ASIC registers
1EE000-1EE7FF F7 Back-up RAM (2K)
100000-10FFFF 80-87 Work RAM (64K)


TurboBooster+ additions

Physical Addresses Segment # Description
1FE800-1FF80F FF ASIC registers (only relating to back-up RAM control)
1EE000-1EE7FF F7 Back-up RAM (2K)


Super CD-ROM2 additions

Physical Addresses Segment # Description
1FE800-1FFBFF FF CD-ROM / ASIC registers
1EE000-1EE7FF F7 Back-up RAM (2K)
100000-10FFFF 80-87 Work RAM (64K)
0D0000-0FFFFF 68-7F Work RAM (192K)
000000-07FFFF 00-3F BIOS ROM (512K)


System Card (v1.x, v2.x) additions

Physical Addresses Segment # Description
000000-03FFFF 00-1F BIOS ROM (256K)


System Card (v3.x) additions

Physical Addresses Segment # Description
1FF800-1FF9FF FF ID locations
0D0000-0FFFFF 68-7F Work RAM (192K)
000000-07FFFF 00-3F BIOS ROM (512K)


Arcade Card DUO additions

Physical Addresses Segment # Description
1FFA00-1FFBFF FF Arcade Card I/O ports
1FF800-1FF9FF FF ID locations
080000-087FFF 40-43 Arcade Card I/O pages


Arcade Card Pro additions

Physical Addresses Segment # Description
1FFA00-1FFBFF FF Arcade Card I/O ports
1FF800-1FF9FF FF ID locations
0D0000-0FFFFF 68-7F Work RAM (192K)
080000-087FFF 40-43 Arcade Card I/O pages
000000-07FFFF 00-3F BIOS ROM (512K)


HuCard/TurboChip "split" format

Physical Addresses Segment # Description
080000-0FFFFF 40-7F Mask ROM #2 (can be 128K, 256K)
000000-07FFFF 00-3F Mask ROM #1 (can be 128K, 256K)

Common sizes are:

384K = ROM #1: 256K + ROM #2: 128K

512K = ROM #1: 256K + ROM #2: 256K


HuCard/TurboChip standard format

Physical Addresses Segment # Description
000000-0FFFFF 00-7F Mask ROM (can be 128K, 256K, 512K)


Street Fighter II CE:' HuCard

Physical Addresses Segment # Description
080000-0FFFFF 40-7F ROM bank (512K of 2MB)
000000-07FFFF 00-3F ROM (512K, fixed)
001FF0-001FF3 00 Bank select registers (write to 1FFx to map ROM bank #x to to the bank area)


"ROMRAM" HuCard (Populous, Tennokoe Bank)

Physical Addresses Segment # Description
 ??????-??????  ?? Battery-backed RAM
000000-0FFFFF 00-3F Game ROM (256K)