View source for Patent 4951038

{{:Patent Style}}

== Patent for Displaying Sprites ==
[b]Note:[/b]
* Here is the [https://www.google.com/patents/US4951038 Original Patent].
* This is a manually transposed version of the patent, please correct any errors you see.
* Terms of significance have been capitalized (to match it's abbreviation) and italicized.
* Many drawings have been replaced by more complete versions from [https://www.google.com/patents/US5319786 Patent 5319786].[br]
* Unintentionally missing information has been copied from [https://www.google.com/patents/US5319786 Patent 5319786].

[pre]
United States Patent Number: [b]4951038[/b]

[b]APPARATUS FOR DISPLAYING A SPRITE ON A SCREEN[/b]

------------------------------------------------------------------------

=== Abstract ===

Apparatus for displaying a sprite on a screen comprises [i]Sprite Attribute Table[/i]s each 
including coordinates indicating a display position of a sprite, a pattern code defining
the sprite in regard to pattern data, and control data defining a display mode of the sprite.
A sprite generator is address in accordance with the pattern code to supply the pattern data
of a sprite to the pattern data buffer.  The sprite is displayed in accordance with the
coordinance thereof on the the screen.  Therefore, the sprite is moved on the screen only by
changing the coordinance of the corresponding [i]Sprite Attribute Table[/i].

4 Claims, 16 Drawing Sheets

------------------------------------------------------------------------

=== Patent Text ===
APPARATUS FOR DISPLAYING A SPRITE ON A SCREEN

==== Field of the Invention ====
The invention related to an apparatus for displaying a sprite on a screen, and more particularly
to an apparatus for displaying a sprite on a screen in which and image unit composed of a
plurality of dots which is called a "sprite" is moved to be displayed on such a screen as a CRT
display and so on.

==== Background of the Invention ====
One of the apparatuses for displaying an image unit composed of a plurality of dots on a CRT 
display is described in Japanese Patent Laid-open No. 11390/1982. In the apparatus for displaying
am image unit on a CRT display, the image unit is moved on the CRT display in accordance with the
subtraction between X value of standard coordinates and a horizontal standard line.  In controlling
signals for two adjacent horizontal scanning lines are alternately written into two line buffer
memories so that image signals read from a character image memory are processed in accordance with
the control signals thus read from the line buffer memories, thereby being displayed on the CRT
display.  The control signals comprise signals of the aforementioned subtractions in the X and Y 
directions so that the image unit is moved smoothly on the CRT display by increasing or decreasing 
the subtraction signal at an appropriate displaying time.

According to the apparatus for displaying an image unit on a CRT display, however, there is a 
disadvantage that a memory region is increased because the character image memory accessed after 
the control signals for the image unit are once written into the parallel line buffer memories.

There is a further disadvantage that enlarging the size of an image unit is difficult to be
performed.

There is a still further disadvantage that, where the number of image units which designated to
be displayed on a DRT display exceeds a predetermined number, an image unit exceeding the
predetermined number is not displayed on the CRT display. 

There is a yet still further disadvantage there there are provided additional registers into which
the so-called "blanking mode" instruction is stored to perform the blanking mode wherein an image
unit is moved from the edge of a CRT display to appear thereon or is moved to the edge therefor
to disappear therefrom.

==== Summary of the Invention ====
Accordingly, it is an object of the invention to provide an apparatus for displaying a sprite on a
screen in which a line buffer memories for storing control signals for a sprite are not necessary 
to be provided.

It is a further object of the invention to provide an apparatus for displaying a sprite on a screen
in which the size of a sprite is easily controlled to be changed on a screen.

It is a still further object of the invention to provide an apparatus for displaying a sprite on a
screen in which, where sprites more than a predetermined number to be displayed on a single
horizontal scanning line are designated, the occurrence of such a designation is indicated.

It is a yet still further object of the invention to provide an apparatus for displaying a sprite
on a screen in which the aforementioned blanking mode is easily performed.

According to the invention, an apparatus for displaying a sprite on a screen comprises, sprite
attribute tabled each for including coordinates indicated a display position of a sprite, a pattern
code defining said sprite in regard to pattern data, and control data defining a display mode of
said sprite, first detection means for comparing a vertical position value of said coordinates of
said sprite to be displayed with a dot clock signal to detect pattern data to be displayed, and
means for controlling said screen to display said sprite to be displayed thereon in accordance with
said pattern data to be displayed.

==== Description of Preferred Embodiments ====

{| class="figure_and_drawing"
|-
|<nowiki>

In [Figure 1], there is shown an apparatus for displaying an image on a screen which is mainly
           composed of a [i]Video Display Controller[/i] (1), a CPU (2), a video color encoder (3), and
           a programmable sound generator (4). The [i]Video Display Controller[/i] (1) supplies the video
           color encoder (3) with image data for a story which are read from a VRAM (7) under the
           control of the CPU (2) reading a program stored in a ROM (5). The CPU (2) controls a
           RAM (6) to store data, calculation or arithmetical results etc. temporarily in
           accordance with a program stored in the ROM (5). The video color encoder (3) is
           supplied with image data to produce RGB analog signals or video color signals including
           luminance signals and color difference signals to which the RGB signals are
           matrix-converted by using color data stored therein. The programmable sound
           generator (4) is controlled by the CPU 2 reading a program stored in the ROM (5) to
           produce audio signals making left and right stereo sounds. The video color signals
           produced at the video color encoder (3) are of composite signals supplied through an
           interface (8) to a television set (9), while the RGB analog signals are directly
           supplied to a CRT of the television set 9 which is used as an exclusive monitor
           apparatus. The left and right analog signals supplied from the programmable sound
           generator (4) are amplified at amplifiers 11a and 11b to make sounds at speakers 12a
           and 12b.
</nowiki>
| [[Image:US4951038-fig1.png | thumb | 500px | [Figure 1] is a block diagram showing an apparatus for displaying an image on a screen in which an apparatus for displaying a sprite on a screen according to the invention is included.]]
|-
| <nowiki>
In [Figure 2A], there is shown the [i]Video Display Controller[/i] (1) transferring data between the
           CPU (2) and VRAM (7) which comprises a control unit (20) including various kinds of
           registers to be described later, an address unit (21), a CPU read/write buffer (22),
           and sprite shift register (24), a background shift register (25), a data bus
           buffer (26), a synchronic circuit (27), and a priority circuit (28).

           The control unit (20) is provided with a [o]BUSY[/o] terminal being "L" to keep the CPU (2)
           writing data into the VRAM (7) or reading data therefrom in a case where the video
           display controller (1) is not in time for the writing or reading of the date, an [o]IRQ[/o]
           terminal supplying an interruption request signal, a CK terminal receiving a clock
           signal of a frequency for one dot (one picture element), a [o]RESET[/o] terminal receiving
           a reset signal for initializing the [i]Video Display Controller[/i] 1, and an EX 8/16
           terminal receiving a data bus width signal for selecting one of 8 and 16 bit data
           buses.

           The address unit (21) is connected to terminals MA0 to MA15 supplying address signals
           for the VRAM (7) which has, for instance, a special address region of 65,536 words. The
           address unit (21), CPU read/write buffer (22), [i]Sprite Attribute Table[/i] (23), sprite
           shift register (24), and background shift register (25) are connected to terminals
           MD0 to MD15 through which data are transferred to and from the VRAM (7).

           The [i]Sprite Attribute Table buffer[/i] (23) is a memory for storing X and Y display
           positions, pattern codes and control data of sprites each composed of 16×16 dots as
           described in more detail later.

           The sprite shift register (24) stores pattern and color data of a sprite read from a
           sprite generator in the VRAM (7) which is accessed in accordance with the pattern
           codes stored in the [i]Sprite Attribute Table[/i] (23) as described in more detail later.

           The background shift register (25) stores pattern data, along with CG color, read 
           from a character generator in the VRAM (7) in accordance with an address based on  a
           character code of a background attribute table in the VRAM (7) which is accessed in
           an address decided by a raster position as also described in more detail later.

           The data bus buffer (26) is connected to terminals D0 to D15 through which data are
           supplied and received. In the [i]Video Display Controller[/i] 1, 8 or 16 bit interface is
           selected to comply with a data width of a system including the CPU (2) wherein the
           terminals D0 to D7 among the terminals D0 to D15 are occupied when the 8 bit
           interface is selected.

           The synchronic circuit (27) is connected to a DISP terminal indicating a display
           period, a [o]VSYNC[/o] terminal from which a vertical synchronous signal for a CRT screen
           is supplied and in which an external vertical synchronous signal is received, and a
           [o]HSYNC[/o] terminal from which a horizontal synchronous signal for a CRT screen is
           supplied and in which an external horizontal synchronous signal is received.


           The priority circuit (28) is connected to terminals VD0 to VD7 through which video
           signals are supplied, and a [i]SP/BG[/i] (VD8) terminal being "H" when the video signals are
           of a sprite and being "L" when the video signals are of a background.

           The aforementioned control unit (20) is also connected to a CS terminal being "L"
           wherein the CPU (2) is able to read data from registers therein and sprite data
           thereinto, a RD terminal receiving a clock signal for the reading thereof, a WR
           terminal receiving a clock signal for the writing thereof, and terminals A0 and A1
           which are connected to address bus of the CPU (2). Further, the [i]Video Display[/i]
           [i]Controller[/i] (1) is provided with a [o]MRD[/o] terminal being "L" when the CPU (2) reads data
           from the VRAM (7), and a [o]MWR[/o] terminal being "L" when the CPU (2) writes data into the
           VRAM (7).
</nowiki>
| [[Image:US4951038-fig2a.png | thumb | 500px | [Figure 2A] is a block diagram showing a [i]Video Display Controller[/i] for the control of writing video signals into VRAM and reading video signals therefrom.]]
|-
| <nowiki>
In [Figure 2B], there is shown an apparatus for displaying a sprite on a screen in an embodiment
           according to the invention wherein the reference numerals 31 and 32 indicate a sprite
           attribute table and sprite generator in the VRAM (7) respectively. The [i]Sprite Attribute[/i]
           table[/i] (31) can include, for instance, sixty four sprites, while the sprite generator (32)
           can include, for instance one thousand and twenty-four sprites.  In the [i]Sprite Attribute[/i]
           [i]Table[/i] (31), addresses of 0 to 63 are assigned to the sixty-four sprites to give a
           priority thereto in the order of the address 0>1>...>62>63.  Each of the sprites in
           composed of 16x16 bits, and includes X and Y coordinates, pattern codes and control
           data. As to each of the sprites, the Y coordinate is compared with a raster signal
           supplied from a scanning raster producing circuit (33) in a coincidence detection
           circuit (34) with whereby sprites each have a Y coordinate coincident with a raster
           signal are stored into a pattern code buffer (35) which can store a maximum of sixteen
           sprites by referring to a corresponding one of the addresses 0 to 63. A selector (36)
           selects a pattern code of the [i]Sprite Attribute Table[/i] (31) in accordance with an address
           stored in the pattern code buffer (35) to access the sprite generator (32) in regard to
           an address which is of a selected pattern code, thereby reading pattern data from the
           sprite generator (32).  The pattern data thus obtained are stored into a pattern data
           buffer (37) along with an X coordinate corresponding thereto read from the [i]Sprite[/i]
           [i]Attribute Table[/i] (31).  The storing of sprites into the pattern code buffer (35) is
           performed at a [i]Horizontal Display Period[/i] preceding to the present horizontal display
           period by one scanning raster, while the storing of the pattern data into the pattern
           data buffer (37) is performed at a following horizontal retrace period.  When a
           scanning raster at which pattern data are displayed has come, the X coordinate thus
           stored in a pattern data buffer (37) is compared with a counted value of a horizontal
           dot clock counter (38) in a coincidence detection circuit (39) whereby pattern data
           having an X coordinate coincidence with the counted value are supplied to a
           parallel/serial converting circuit (40). In the parallel/serial converting circuit (40),
           parallel pattern data are converted into serial pattern data which are supplied through
           a gate circuit (42) is controlled to be turned on and off in accordance with the content
           of a starting coordinates registration circuit (43) by the CPU (2).  The content thereof
           is X and Y coordinates by which the starting coordinates of a display region is defined
           on a display screen.
</nowiki>
| [[Image:US4951038-fig2b.png | thumb | 500px | [Figure 2B] is a block diagram showing an apparatus for displaying a sprite on a screen in an embodiment according to the invention.]]
|-
| <nowiki>
In [Figures 3A to 3U], there are shown various kinds of registers included in the Control Unit (20)
           of the Video Display Controller (1).

   (a) Address Register ([Figure 3A])
          A register number "AR" is exclusive written into the address register designating one of
          the memory address write register to DMA VRAM-SATB source address register as shown in
          Figures 3C to 3U so that data are writing into the [i]Video Display Controller[/i] (1) under the
          condition that the A1 and [o]CS[/o] terminals thereof are "L".

          In a case where 16 bit data bus is selected, the EX 8/[o]16[/o] terminal is "0", the A1
          terminal is "0", the "R/W" terminal is "W", and the A0 terminal is no matter.

          In a case where 8 bit data bus is selected, the EX 8/[o]16[/o] terminal is "1", the A0
          and A1 terminals are "0", and the "R/W" terminal is "W".
</nowiki>
| [[Image:US5319786-fig3a.png | thumb | 500px]]
|-
| <nowiki>
   (b) Status Register ([Figure 3B])
          A bit corresponding to one of interruption jobs is set to be "H" in the status register
          to make the interruption active when a cause of the interruption which is enabled by an
          interruption permission bit of a [i]Control Register[/i] and [i]DMA Control Register[/i] as showing in
          Figures 3G and 3Q is occurred.  When the status is read from the status register, the
          corresponding bit is cleared automatically.

          The status indicating bits are as follows.

          (1) bit 0 (CR) - collision of sprites
              It is indicated that the sprite number 0 of a sprite is collided with any one of the
              sprite numbers 1 to 63 of sprites.

          (2) bit 1 (OR) - more sprites than a predetermined number
              (2.1) a case where more than 17 sprites are detected on a single raster line.
              (2.2) a case where data of a sprites which is designated are not transferred to a
                    data buffer in a horizontal trance period.
              (2.3) a case where a bit of CGX in control data of a sprite by which two sprites are
                    joined in a horizontal direction is set so that data of the sprites are not
                    transferred to a data buffer.

          (3) bit 2 (PR) - detection of raster
              It is indicated that a value of a raster counter becomes a predetermined value of a
              raster detecting register.

          (4) bit 4 (DS) - finishing of DMA transfer
              It is indicated that data transfer between the VRAM and [i]Sprite Attribute Table[/i]
              buffer (23) is finished.

          (5) bit 4 (DV) - finishing of DMA transfer
              It is indicated between two regions of VRAM (7) is finished.

          (6) bit 5 (VD) - vertical retrace period
              It is indicated that the VRAM (7) accessed for the writing or reading of data by the
              CPU (2) so that the [o]BUSY[/o] terminals is "0".
</nowiki>
| [[Image:US5319786-fig3b.png | thumb | 500px]]
|-
| <nowiki>
   (c) Memory Address Write Register (register name "00", [Figure 3C])
          A starting address "MAWR" is written into the memory address write register so that the
          writing of data begins at the starting address of the VRAM (7).
</nowiki>
| [[Image:US5319786-fig3c.png | thumb | 500px]]
|-
| <nowiki>
   (d) Memory Address Read Register (register number "01", [Figure 3D])
          A starting address "MARR" is written into the memory address read register.  When the
          upper byte of the starting address is written thereinto, data are begun to be read from
          the starting address of the VRAM (7) so that data thus read are written into a VRAM data
          read register as showing in Figure 3F.  There after, the starting address "MARR" is
          automatically incremented by one.
</nowiki>
| [[Image:US5319786-fig3d.png | thumb | 500px | [Figure 3D] Memory Address Read Register (MARR)]]
|-
| <nowiki>
   (e) VRAM Data Write Register (register number "02", [Figure 3E])
          Data which are transferred from the CPU (2) to the VRAM (7) are written into the VRAM data
          write register.  When the upper byte of the data "VWR" is written thereinto, the video
          display controller (1) begins to write the data into the VRAM (7) and the address "MAWR" of
          the memory address write register is automatically incremented by one upon writing of the
          data.
</nowiki>
| [[Image:US5319786-fig3e.png | thumb | 500px | [Figure 3E] VRAM Data Write Register (VDWR)]]
|-
| <nowiki>
   (f) VRAM Data Read Register (register number "02", [Figure 3F])
          Data which are transferred from the VRAM (7) to the CPU (2) are written into the VRAM data
          read register.  When the upper byte of the data "VRR" is read therefrom, the reading of
          data is performed at the following address of the VRAM (7).
</nowiki>
| [[Image:US5319786-fig3f.png | thumb | 500px | [Figure 3F] VRAM Data Read Register (VDRR)]]
|-
| <nowiki>
   (g) Control Register (register number "05", [Figure 3G])
          An operating mode of the [i]Video Display Controller[/i] (1) is controlled in accordance with the
          following bits of the [i]Control Register[/i].

          (1) bits 0 to 3 (IE) - enable of interruption request
              (1.1) bit 0 - collision detection of sprites
              (1.2) bit 1 - excess number detection of sprites
              (1.3) bit 2 - raster detection
              (1.4) bit 3 - detection of vertical retrace period

          (2) bits 4 and 5 (EX) - external synchronism

        </nowiki>[[Image:US4951038-chart1.png | 500px]]
<nowiki>
          (3) bit 6 (SB) - sprite blanking
              It is decided whether a sprite should be displayed on a screen or not.
              The control of the bit is effective in the following [i]Horizontal Display Period[/i].
              (3.1) "0" - blanking of a sprite
              (3.2) "1" - display of a sprite

          (4) bit 7 (BB) - background blanking
              It is decided whether background should be displayed on a screen or not.
              The control of the bit is effective in the following [i]Horizontal Display Period[/i].
              (4.1) "0" - blanking of background
              (4.2) "1" - display of background.

          (3.4) As a result, when bits 6 and 7 are both "0", there is a resulted "burst mode" in
              which the following operations can be performed.
              (3.4.1) The access to the VRAM (7) is not performed for a display, but the VRAM (7) is
                      accessed by the CPU (2).
              (3.4.2) DMA between two regions of the VRAM (7) is possible to be performed at any
                      time.

              In such occasions, the terminals VD0 and VD7 are all "L" while the [i]SP/BG[/i] terminal is
              "H". On the other hand, when the bits 6 and 7 are both "1", there is released from
              the "burst mode".

          (5) bits 8 and 9 (TE) - selection of DISP terminal outputs

        </nowiki>[[Image:US4951038-chart3.png | 500px]]
<nowiki>
          (6) bit 10 (DR) - dynamic RAM refresh
              Refresh address is supplied from the terminals MA0 to MA15 upon the setting of the
              bit in a case where VRAM dot with is of 2 dots or 4 dots for background in a memory
              width register as showing in Figure 3K.

          (7) bits 11 and 12 (IW) - increment width selection of memory address write register or
              memory address read register
              A width which is incremented in address is selected as follows.

        </nowiki>[[Image:US4951038-chart2.png | 500px]]
<nowiki>
              In a case of 8 bit access, an address is incremented upon the upper byte.
</nowiki>
| [[Image:US5319786-fig3g.png | thumb | 500px | [Figure 3G] Control Register (CR)]]
|-
| <nowiki>
   (h) Raster Detecting Register (register number "06", [Figure 3H])
          A raster number "RCR" at which an interruption job is performed is written into the
          raster detecting register.  An interruption signal is produced when a value of a raster
          counter is equal to the raster number "RCR".  The raster counter is preset to be "64" at
          a preceding scanning raster line to a display starting raster line as described in more
          detail later, and is increased at each raster line by one.
</nowiki>
| [[Image:US5319786-fig3h.png | thumb | 500px | [Figure 3H] Raster Detecting Register (RDR)]]
|-
| <nowiki>
   (i) BGX Scroll Register (register number "07", [Figure 3I])
          The BGX scroll register is used for a horizontal scroll of background on a screen.  When
          a content "BXR" is rewritten therein, the content is effective in the following raster
          line.
</nowiki>
| [[Image:US5319786-fig3i.png | thumb | 500px | [Figure 3I] BGX Scroll Register (BGX)]]
|-
| <nowiki>
   (j) BGY Scroll Register (register number "08", [Figure 3J])
          The BGY scroll register is used for a vertical scroll of background on a screen.  When a
          content "BYR" is rewritten therein, the content is effective to be as "BYR+1" in the
          following raster line.
</nowiki>
| [[Image:US5319786-fig3j.png | thumb | 500px | [Figure 3J] BGY Scroll Register (BGY)]]
|-
| <nowiki>
   (k) Memory Width Register (register number "09", [Figure 3K])
          (1) bits 0 and 1 (VM) - VRAM dot width
              A dot width in which an access to the background attribute table and character
              generator, DMA and access of the CPU (2) to the VRAM (7) during a horizontal display
              period are performed is written into the bits of the memory width register.  The dot
              width is decided dependent on a memory speed of the VRAM (7).  When the bits 0 and 1
              are re-written therein, the content is effective at the beginning of a vertical
              retrace period.

        </nowiki>[[Image:US4951038-chart4.png | 500px]]
<nowiki>
              "BAT" is for background attribute table, and "CG" is for character generator.

          (2) bits 2 and 3 (SM) - sprite dot width
              A dot width which an access to the sprite generator is performed during a horizontal
              retrace period is written into the bits of the memory width register.

        </nowiki>[[Image:US4951038-chart5.png | 500px]]
<nowiki>
          (3) bits 4 to 6 (SCREEN)
              The number of character in X and Y directions of a fictitious screen is decided
              dependent on the content of the bits.  When a content is effective at the beginning
              of a vertical retrace period.

        </nowiki>[[Image:US4951038-chart7.png | 500px]]
<nowiki>
          (4) bit 4 (CM) - CG mode
              When a VRAM dot width is of 4 dots, a color block of a character generator is
              changed dependent on the bit. A content is writtent into the bit, the content is
              effective in the following raster line.
</nowiki>
| [[Image:US5319786-fig3k.png | thumb | 500px | [Figure 3K] Memory Width Register (MWR)]]
|-
| <nowiki>
   (l) Horizontal Synchronous Register (register number "0A", [Figure 3L])
          (1) bits 1 to 4 (HSW) - horizontal synchronous pulse
              A pulse width of "L" level of a horizontal synchronous pulse is set as an unit of a
              character cycle. One of 1 to 32 is selected by using 5 bits to comply with the
              specification of a CRT display.

          (2) bits 8 to 14 (HDS) - starting position of horizontal display
              A period between a rising edge of a character cycle.  An optimum position in a
              horizontal direction on a CRT display is decided by a content of the 7 bits.  When
              it is assumed that a horizontal display position (horizontal back porch) is "N",
              "N-1" is written into HDS bits.
</nowiki>
| [[Image:US5319786-fig3l.png | thumb | 500px | [Figure 3L] Horizontal Synchronous Register (HSR)]]
|-
| <nowiki>
   (m) Horizontal Display Register (register number "0B", [Figure 3M])
          (1) bits 0 to 6 (HDW) - horizontal display width
              A display period in each raster line is set as an unit of a character cycle, and is
              decided in accordance with the number of characters in the horizontal direction on a
              CRT screen dependent on a content of the 7 bits.  If it is assumed that a horizontal
              display position is "N", "N-1" is written into HDW bits.

          (2) bits 8 to 11 (HDE) - horizontal display ending position
              A period between an ending of a [i]Horizontal Display Period[/i] and a rising edge of a
              horizontal synchronous signal is set as an unit of a character cycle.  An optimum
              position of a horizontal display is set on a CRT display by the 7 bits.  When it is
              assumed that a horizontal display ending position (horizontal back porch) is "N",
              "N-1" is written into HDE bits.
</nowiki>
| [[Image:US5319786-fig3m.png | thumb | 500px | [Figure 3M] Horizontal Display Register (HDR)]]
|-
| <nowiki>
   (n) Vertical Synchronous Register (register number "0C", [Figure 3N])
          (1) bits 0 to 4 (VSW) - vertical synchronous pulse width
              A pulse width of a vertical synchronous signal is decided in a width of "L" level
              as a unit of a raster line.  One of 1 to 32 is selected to comply with a
              specification of a CRT display.

          (2) bits 8 to 15 (VDS) - vertical display starting position
              A period between a rising edge of a vertical synchronous signal and a vertical
              synchronous starting position is set as an unit of a raster line.  When it is assumed
              that a vertical display starting position (vertical back porch) is "N", "N-2" is
              written into the bits.
</nowiki>
| [[Image:US5319786-fig3n.png | thumb | 500px | [Figure 3N] Vertical Synchronous Register (VSR)]]
|-
| <nowiki>
   (o) Vertical Display Register (register number "0D", [Figure 3O])
          A vertical display period (display region) is set as an unit of a raster line.  A
          vertical display width is decided in accordance with the number of raster lines to be
          displayed on a CRT display which is defined by a content of the 9 bits.  When it is
          assumed that a vertical display width is "N", "N-1" is written into the VDW bits.
</nowiki>
| [[Image:US5319786-fig3o.png | thumb | 500px | [Figure 3O] Vertical Display Register / Vertical Display Width (VDW)]]
|-
| <nowiki>
   (p) Vertical Display Ending Position Register (register number "0E", [Figure 3P])
          A period between a vertical display ending position and a rising edge of a vertical
          synchronous signal is set as an unit of a raster line.  When it is assumed that a
          vertical optimum position (vertical front porch) is "N" to be defined by the 8 bits,
          "N" is written into the VCR bits.
</nowiki>
| [[Image:US5319786-fig3p.png | thumb | 500px | [Figure 3P] Vertical Display Ending Position Register / Vertical C..... R..... (VCR)]]
|-
| <nowiki>
   (q) DMA Control Register (register number "0F", [Figure 3Q])
          (1) bit 0 (DSC) - enable an interruption at the finishing of transfer between the
              VRAM (7) and [i]Sprite Attribute Table[/i] buffer (23)
              It is decided whether or not an interruption is enabled at the finishing time of
              the transfer.
              (1.1) "0" - disable
              (1.2) "1" - enabled

          (2) bit 1 (DVC) - enable an interruption at the finishing of transfer between two
              regions of the VRAM (7).
              It is decided whether or not an interruption is enabled finishing time of the
              transfer
              (2.1) "0" - disable
              (2.2) "1" - enabled

          (3) bit 2 (SI/D) - increment/decrement of a source address
              One of automatical increment and decrement of a source address is selected in a
              transfer between two regions of VRAM (7).
              (3.1) "0" - disable
              (3.2) "1" - enabled

          (4) bit 3 (DI/D) - One of automatical increment and decrement of a destination
              address is selected in a transfer between two regions of VRAM (7).
              (4.1) "0"--increment
              (4.2) "1"--decrement

          (5) bit 4 (DSR)--repetition of a transfer between the VRAM (7) and Sprite Attribute
              Table buffer (23).
              It is decided whether or not a repetition of a transfer between the VRAM (7)
              and [i]Sprite Attribute Table[/i] buffer (23) is enabled.
              (5.1) "0"--disable
              (5.2) "1"--enabled

          (6) bit 5 (DSR) - repetition of a transfer between the VRAM (7) and the Sprite
              Attribute Table buffer (23) is enabled.
              (6.1) "0"--disable
              (6.2) "1"--enabled
</nowiki>
| [[Image:US5319786-fig3q.png | thumb | 500px | [Figure 3Q] DMA Control Register (DCR)]]
|-
| <nowiki>
   (r) DMA Source Address Register (register number "10", [Figure 3R])
          A starting address of a source address is allocated in a transfer between two regions
          of the VRAM (7).
</nowiki>
| [[Image:US5319786-fig3r.png | thumb | 500px | [Figure 3R] DMA Source Address Register (SOUR)]]
|-
| <nowiki>
   (s) DMA Destination Address Register (register number "11", [Figure 3S])
          A starting address of a destination address is allocated in a transfer between two
          regions of the VRAM (7).
</nowiki>
| [[Image:US5319786-fig3s.png | thumb | 500px | [Figure 3S] DMA Destination Address Register (DESR)]]
|-
| <nowiki>
   (t) DMA Block Length Register (register "12", [Figure 3T])
          A length of a block is defined in a transfer between two regions of the VRAM (7).
</nowiki>
| [[Image:US5319786-fig3t.png | thumb | 500px | [Figure 3T] DMA Block Length Register (LENR)]]
|-
| <nowiki>
   (u) DMA VRAM-SATB Source Address Register (register number "13", [Figure 3U])
          A starting address of a source address is allocated in a transfer between the VRAM (7)
          and [i]Sprite Attribute Table[/i]d buffer (23).
</nowiki>
| [[Image:US5319786-fig3u.png | thumb | 500px | [Figure 3U] DMA VRAM-SAT Source Address Register (DVSSR)]]
|-
| <nowiki>
In [Figure 4A], there is shown an address in a background attribute table for a character of a
          fictitious screen.  A character and color to be displayed at each character position
          are stared in a background attribute table.  A predetermined number of background
          attibute tables are stored in a region the first address of which is "0" in the VRAM (7).
          The fictitious screen shown therein which is one example is of 32x32 character
          (1F[sub]16[/sub] = 32[sub]10[/sub]).
</nowiki>
| [[Image:US4951038-fig4a.png | thumb | 500px | [Figure 4A] is an explanatory diagram showing a fictitious screen in the embodiment according to the invention.]]
|-
| <nowiki>
In [Figure 4B], there is shown a screen which is framed by writing respective predetermined
          values into the aforementioned horizontal synchronous register, horizontal display
          register, vertical synchronous register and vertical display register shown in
          [Figures 3M-3O].  Although the respective predetermined values for the registers are
          not explained here, a display region is defined in accordance with "HDW+1" in the
          horizontal display register "VDW+1" in the vertical display register.  In the
          embodiment, the starting coordinates (x, y) for the display region is indicated to
          be (32, 64).
</nowiki>
| [[Image:US5319786-fig4b.png | thumb | 500px | [Figure 4B] is an explanatory diagram showing a display region on a screen in the embodiment according to the invention.]]
|-
| <nowiki>
In [Figures 5A/B] there are shown background attribute tables (BATs) in the VRAM (7) each of
          16 bits to have a character code of lower 12 bits for designating a CG color code.
</nowiki>
| [[Image:US5319786-fig5.png | thumb | 500px | [Figures 5A/B] are explanatory diagrams showing a background attribute table in the VRAM in the embodiment according to the invention.]]
|-
| <nowiki>
In [Figures 6A/B], there are shown [i]Sprite Attribute Table[/i]d (SATs) (31) in the VRAM along with the
          sprite generator region (32).  Each of the [i]Sprite Attribute Table[/i]s (31) is composed of
          16x4 bits, that is, four words to define a sprite.  Therefore, sixty four sprites are
          defined by 256 words.  In the [i]Sprite Attribute Table[/i], lower 10 bits in the first word
          designate a horizontal position (0 to 1023) of a sprite.  For this purpose, one of 
          0 to 1023 is written into a X coordinate therein.  In the same manner, lower 10 bits
          in the second word designate a vertical position (0 to 1023) of a sprite, and one of
          0 to 1023 is written into a Y coordinate therein.  On the other hand, lower 11 bits in
          the third word is for a pattern number which is an address for a sprite generator (32),
          while the fourth word is for control bits including [o]Y[/o] (X[sub]15[/sub]), CGY 
          (two bits of X[sub]13[/sub] and X[sub]12[/sub]), [o]X[/o] (X[sub]11[/sub]), CGX (X[sub]8[/sub]),
          BG/SP (X[sub]7[/sub]) and a color for a sprite (four bits of X[sub]3[/sub] to X[sub]0[/sub]) in
          the direction of MSB to LSB.

              The control bits are defined as follows.
                (1) setting of [o]Y[/o]
                    A sprite is displayed to be reversed in the Y direction.

                (2) setting of CGX
                    Two sprites consisting of a sprite to be addressed in the sprite generator (32)
                    and the other sprite of the following address are displayed to be joined in
                    the horizontal direction

                (3) setting of [o]X[/o]
                    A sprite is displayed to be reversed in the X direction.

                (4) setting of CGY
                    The two bits X[sub]13[/sub] and X[sub]12[/sub] define three modes to be
                    described in more detail later.

        </nowiki>[[Image:US4951038-chart6.png | 500px]]
<nowiki>
                (5) BG/SP
                    The bit X[sub]7[/sub] designates a priority between displayed of background
                    and sprite
                    (5.1) "0" - background
                    (5.2) "1" - sprite

                (6) sprite color
                    The bits X[sub]3[/sub] to X[sub]0[/sub] into an area color of a sprite.
                    Each sprite has four facets to be called SG0 to SG3 each being of 16x16 dots
                    so that one sprite occupies 64 words.

          The writing of data into a [i]Sprite Attribute Table[/i] (31) is performed such that the data
          are not transferred from the CPU (2) directly to the VRAM (7), but in DMA transfer from
          the CPU (2) to the [i]Sprite Attribute Table[/i] buffer (23).

          In operation, a sprite [i]SP[/i] having standard coordinates (2,2) is displayed on a display
          screen (9) having 1024 display dots respectively in the X and Y directions as shown in
          [Figure 7]. In displaying the sprite [i]SP[/i] thereon, the Y coordinates of the sixty-four
          [i]Sprite Attribute Table[/i]s (31) are compared in turn with a raster signal supplied from
          the scanning raster signal producing circuit (33) at the coincidence detection
          circuit (34) to pick up sprites each having a Y coordinate "2" which is then stored
          in its stripe number among the stripe numbers 0 to 63 into the pattern code buffer (35)
          when a [i]Horizontal Display Period[/i] of a scanning raster number "1" is started in the
          apparatus as shown in [Figure 2B]. In this occasion, sixteen of sprites can be stored
          in the pattern code buffer (35) at the maximum. During a horizontal retrace period
          before which a scanning raster number "1" is finished and after which a scanning
          raster number "2" is started, address signals are produced in the selector (36) in
          accordance with the sprite numbers stored in the pattern code buffer (35) and pattern
          codes in the [i]Sprite Attribute Table[/i]s (31) so that pattern data are read from the
          sprite generator (32) in accordance with the address signals thus produced. The
          pattern data are stored in the pattern data buffer 37 along with X coordinates
          corresponding thereto in the [i]Sprite Attribute Table[/i]s 31. When a horizontal display
          period of the scanning raster number "2" is started, the X coordinates stored in the
          pattern data buffer (37) are compared with counted values of the horizontal dot clock
          counter (38) at the coincidence detection circuit (39). In the comparison, pattern
          data for the sprite [i]SP[/i] are read to be supplied to the parallel/serial converting
          circuit (40) from the pattern data buffer (37) when the counted value corresponds to
          X = 2. The parallel pattern data are converted into serial pattern data in the
          parallel/serial converting circuit (40) so that a picture element (2, 2) of the sprite
          [i]SP[/i] is displayed on the CRT screen (9) in accordance with the serial pattern data
          passed through the gate circuit (42). Thereafter, fifteen picture elements (3, 2),
          (4, 2) - (17, 2) are displayed thereon to complete the display of the sprite [i]SP[/i] on the
          Y = 2 raster line. As a matter of course, control data of the sprite attribute
          table (31) corresponding to the sprite [i]SP[/i] are used to control the display thereof. In
          moving the sprite [i]SP[/i] having the standard coordinates (2, 2) to a display position
          having a standard coordinates (X, Y) to be a sprite SP', the X and Y coordinates
          (2, 2) of the [i]Sprite Attribute Table[/i] 31 corresponding to the sprite [i]SP[/i] are only
          changed to be X and Y coordinates (x, y) without changing contents of the sprite
          generator 32 and necessitating the redefinition of a pattern. The sprites [i]SP[/i] and [i]SP[/i]'
          are displayed in accordance with the combination of more than one facets among the
          four facets SG0 to SG3.

          Such a combination of facets SG0 to SG3 is shown in [Figure 8].  For instance all of
          the four faces SG0 to SG3 are combined to display a sprite sp[sub]1[/sub], while the facets
          SG0 to SG1 are combined to display a sprite sp[sub]2[/sub]. As clearly understood from the
          example, 24 display patterns are obtained in accordance with the calculation
          "4x3x2=24" so that a desired pattern can be selected from 24 patterns in accordance with
          control data in a [i]Sprite Attribute Table[/i].  The four facets SG0 to SG3 are of different
          colors each to be designated by an area color code.

          Next, the aforementioned CGX and CGY defined by control data in a sprite attribute
          table (31) are explained.
</nowiki>
| [[Image:US5319786-fig6.png | thumb | 500px | [Figures 6A/6B] are explanatory diagrams showing a [i]Sprite Attribute Table[/i] in the VRAM in the embodiment according to the invention.]]
|-
| [[Image:US5319786-fig7.png | thumb | 500px | [Figure 7] is an explanatory diagram explaining a first operation in which a sprite is moved on a screen in the embodiment according to the invention.]]
|-
| <nowiki>
In [Figure 9], there is shown a sprite generator (SG) (32) comprising pattern data A, B, C--. In
          accordance with the definition of CGX and CGY as explained before, various kinds of
          sprite patterns each having a different color and size from others are obtained
          without increasing a memorizing area of the sprite generator (32) as shown in
          [Figures 10A-E].

          Further, [o]X[/o], [o]Y[/o], CGX and CGY are explained more in conjunction with
          [Figures 11A-C and 12A-C].
</nowiki>
| [[Image:US4951038-fig8&9.png | thumb | 500px | [Figure 8] is an explanatory diagram explaining a second operation in which a plurality of facets are combined to provide a sprite in the embodiment according to the invention.[br][br][Figure 9] is an explanatory diagram showing a sprite generator in the embodiment according to the invention.]]
|-
| [[Image:US4951038-fig10.png | thumb | 500px | [Figures 10A-E] are explanatory diagrams showing a third operation in which a size of a sprite is enlarged in the embodiment according to the invention.]]
|-
| <nowiki>
In [Figure 11A], when a bit [o]X[/o] in a [i]Sprite Attribute Table[/i] (31) is set to be "1", a sprite
          is displayed to be reversed in a left-side right manner.  On the other hand, when
          a bit [o]Y[/o] in the [i]Sprite Attribute Table[/i] (31) is set to be "1", the sprite is displayed
          to be reversed in an upside down manner.  As a matter of course, when the bits [o]X[/o]
          and [o]Y[/o] are set to be "1", the sprite is displayed to be reversed in a left-size
          right and upside down manner.
</nowiki>
| [[Image:US4951038-fig11a.png | thumb | 500px | [Figures 11A-C and 12A-C] are explanatory diagrams showing a fourth operation in which a sprite is reversed, and a plurality of sprites are combined to enlarge the size thereof in the embodiment according to the invention.]]
|-
| <nowiki>
In [Figures 11B/C], a CGX control mode as explained before is again explained.  When a CGX bit
          is set to be "1", a sprite of an address designated by a pattern code in a sprite
          attribute table and a sprite of a preceding of following address to the designated
          address are displayed to be joined in the X direction.  To be more concrete, if the
          designated address is "00001000110" as shown in [Figure 11B], a sprite of an address
          "00001000100" in which the bit X' is changed from "1" to "0" is positioned to the
          left, and a sprite of the designated address in which the bit X[sub]1[/sub] is "1"
          is positioned to the right so that a sprite of the CGX mode is obtained as shown in
          [Figure 11C] wherein two patterns of [o]X[/o]=0 and [o]Y[/o] = 0 and [o]X[/o]=1 and
          [o]Y[/o] = 0 are displayed.
</nowiki>
| [[Image:US4951038-fig11bc.png | thumb | 500px | [Figures 11A-C and 12A-C] are explanatory diagrams showing a fourth operation in which a sprite is reversed, and a plurality of sprites are combined to enlarge the size thereof in the embodiment according to the invention.]]
|-
| <nowiki>
In [Figures 12A/B/C], a CGY display mode as briefly explained before is again explained.  In the
          CGY display mode, two bits X[sub]3[/sub] and X[sub]2[/sub] of a pattern code in a
          [i]Sprite Attribute Table[/i] are controlled so as to be (0, 0), (0, 1), (1, 0) and (1, 1).
          Therefore if it is "00001000110", an address map of a sprite generator is illustrated
          as shown in [Figure 12A].  As a result, a sprite is displayed in 4CGY mode as shown
          in [Figure 12B] wherein [o]X[/o] and [o]Y[/o] bits are not set to be "1" and in
          [Figure 2C] wherein X is not set to be "1", while Y bit set to be "1".

          As clearly understood from the CGX and CGY display modes, a pattern size of a sprite
          is of 2x16x16 dots in the CGX mode, and that of a sprite is of 4x16x16 dots in the
          4CGY mode so that the starting coordinates (x, y) of the display region are set to be
          (32, 64) in the embodiment.  For the reason, the starting coordinates may be changed
          dependent on CGX and CGY modes.


          Referring back to [Figure 2B], the starting coordinates (x, y) of the display region
          defined by (HDW+1)x (VDW+1) as explained in [Figures 4B] is set in the start
          coordinates registration circuit (43) to be (32, 64).  During the horizontals display
          period of a raster number "1", a counter value of the horizontal dot clock counter (38)
          and an X coordinates equal to the counted value are read from the pattern data
          buffer (37) to be converted from parallel to serial in the parallel/serial converting
          circuit (40).
          In this occasion, all of Y coordinates of the sprites are "1", while each of the X
          coordinates of the sprites ranges from X to X+15, where X is a counted value of the
          horizontal dot clock counter (38) because each sprite of 16x16 dots.  Therefore, when
          the CGX display mode is performed, that ranges from X to X+31.  Due to the fact that
          the Y coordinates are all "1", the serial pattern data can not be passed through the
          gate circuit (42) which is controlled in accordance with the starting coordinates
          (32, 64) of the start coordinates registration circuit (43) by the CPU (2) regardless
          of X coordinates thereof so that the pattern data are not displayed on the CRT
          screen (9).  In this manner, the control of sassing serial pattern data through the
          gate circuit (42) is performed in regard to the raster number 2, 3-k-by the CPU (2).

          Thus, serial pattern data having a horizontal display position larger than 32 and
          vertical display position larger than 64 are passed through the gate circuit (42) to
          be displayed on the CRT screen (9).  As a result, the blanking of a sprite can be
          performed so that a sprite is appeared smoothly from the top, bottom, left and right
          onto the CRT screen, and disappeared in the same manner.

          In the control of displaying a sprites, the number of sprites to be designated in
          the coincidence detection circuit (34) is checked by the CPU (2).  When the CPU (2)
          detects the number to be more than a predetermined number, sixteen in the embodiment,
          a warning signal produced therefrom to indicate the occurrence on the CRT screen (9).
          In other words, the seventeenth sprite which is designated to be displayed is not
          displayed on the CRT screen (9).

          In a case where all of pattern data for sprites to be designated are no transferred
          from the sprite generator (32) to the pattern data buffer (37) in a horizontal retrace
          period, it is understood in the CPU (2) that pattern data exceed a limitation of a
          display on the CRT screen (9).  Such an excess pattern data are liable to be read from
          the sprite generator (32), for instance, in a case of CGX display mode as explained
          before.
</nowiki>
| [[Image:US4951038-fig12.png | thumb | 500px | [Figures 11A-C and 12A-C] are explanatory diagrams showing a fourth operation in which a sprite is reversed, and a plurality of sprites are combined to enlarge the size thereof in the embodiment according to the invention.]]
|}
------------------------------------------------------------------------

=== Claims ===
<nowiki>
Although the invention has been described to respect to specific embodiment for complete and
clear disclosure the appended claims are not to thus limited but are to be constructed as
embodying all modification and alternative constructions that may occur to one skilled in the
art which fairly fall within th basic teaching herein set forth.

What is claimed is:

1. An apparatus for displaying a sprite on the display screen comprising:

   [i]Sprite Attribute Table[/i]s each including coordinates indicating a display position of a
   sprite, a pattern code defining said sprite in regard to pattern data, and control data
   defining a display mode of said sprite;

   first detection means for comparing a vertical position value of said coordinates with a
   raster number to detect a sprite to be displayed;

   a sprite generator storing pattern data of said sprite;

   second detection means for comparing a horizontal position value of said coordinates of
   said sprite to be displayed with a dot clock signal to detect pattern data to be displayed;

   a pattern data buffer for storing pattern data of said sprite to be displayed in accordance
   with the reading thereof from said sprite generator;

   means for storing standard coordinates of a display region on said screen;

   a gate circuit for providing said pattern data stored in said pattern data buffer to said
   screen; ands

   means for controlling said screen to display said sprite to be displayed thereon in
   accordance with said pattern data to be displayed, wherein said controlling means decides
   selectively an allowance of an inhibition of said transmission of said pattern data in
   accordance with a comparison of said coordinates indicating said display position with said
   standard coordinates.

2. An apparatus for displaying a sprite on a display screen according to claim wherein:

     said storing means stored starting coordinates of said display region; and

     said controlling means inhibits said transmission of said pattern data when said
     coordinates indicate said display position is less than said starting coordinates.

3. An apparatus for displaying a sprite on a display screen according to claim 2, wherein:

     said storing means stores said starting coordinates determined in accordance with
     contents of a Horizontal Period Register, a Vertical Synchronism Register, and a
     [i]Vertical Display Register[/i].

4. An apparatus for displaying a sprite on video display responsive to display scan
   information supplied by a Vertical Scanning Raster Register and a Horizontal Dot Clock
   counter, comprising:

     a memory for storing a [i]Sprite Attribute Table[/i], said table including coordinates
     indicating a display position of a sprite, a pattern code defining said sprite, and
     display control data defining a display mode of said sprite;

     a first coincidence detector for comparing a vertical position value of said
     coordinates store in said memory with a raster number supplied by the vertical
     scanning register to detect a sprite to be displayed;

     a sprite generator storing pattern data of said sprite to be displayed;

     a pattern data buffer for storing pattern data from said sprite generator of said
     sprite to be displayed;

     a second coincidence detector for comparing a horizontal position value of said
     coordinates of said sprite to be displayed from said memory with a dot clock signal
     supplied by the horizontal dot clock counter and, in response, supplying a portion
     of said pattern data to be displayed received from said pattern data buffer;

     a start coordinates registration circuit for storing boundary coordinates defining a
     display region;

     a controller receiving said boundary coordinates from said start coordinates
     registration circuit and, in response to detecting a display position within said
     boundary coordinates, generating a display control signal; and

     a gate circuit for receiving said portion of said pattern data from said pattern data
     data and, in response to said display display control signal from said controller,
     providing said portion of said pattern data to said video display.

</nowiki>
[/pre]