Difference between revisions of "Patent 4951038"
Line 97: | Line 97: | ||
In [Figure 1], there is shown an apparatus for displaying an image on a screen which is mainly | In [Figure 1], there is shown an apparatus for displaying an image on a screen which is mainly | ||
− | composed of a | + | composed of a [i]Video Display Controller[/i] (1), a CPU (2), a video color encoder (3), and |
− | a programmable sound generator (4). The | + | a programmable sound generator (4). The [i]Video Display Controller[/i] (1) supplies the video |
color encoder (3) with image data for a story which are read from a VRAM (7) under the | color encoder (3) with image data for a story which are read from a VRAM (7) under the | ||
control of the CPU (2) reading a program stored in a ROM (5). The CPU (2) controls a | control of the CPU (2) reading a program stored in a ROM (5). The CPU (2) controls a | ||
Line 118: | Line 118: | ||
|- | |- | ||
| <nowiki> | | <nowiki> | ||
− | In [Figure 2A], there is shown the | + | In [Figure 2A], there is shown the [i]Video Display Controller[/i] (1) transferring data between the |
CPU (2) and VRAM (7) which comprises a control unit (20) including various kinds of | CPU (2) and VRAM (7) which comprises a control unit (20) including various kinds of | ||
registers to be described later, an address unit (21), a CPU read/write buffer (22), | registers to be described later, an address unit (21), a CPU read/write buffer (22), | ||
Line 129: | Line 129: | ||
terminal supplying an interruption request signal, a CK terminal receiving a clock | terminal supplying an interruption request signal, a CK terminal receiving a clock | ||
signal of a frequency for one dot (one picture element), a [o]RESET[/o] terminal receiving | signal of a frequency for one dot (one picture element), a [o]RESET[/o] terminal receiving | ||
− | a reset signal for initializing the | + | a reset signal for initializing the [i]Video Display Controller[/i] 1, and an EX 8/16 |
terminal receiving a data bus width signal for selecting one of 8 and 16 bit data | terminal receiving a data bus width signal for selecting one of 8 and 16 bit data | ||
buses. | buses. | ||
Line 135: | Line 135: | ||
The address unit (21) is connected to terminals MA0 to MA15 supplying address signals | The address unit (21) is connected to terminals MA0 to MA15 supplying address signals | ||
for the VRAM (7) which has, for instance, a special address region of 65,536 words. The | for the VRAM (7) which has, for instance, a special address region of 65,536 words. The | ||
− | address unit (21), CPU read/write buffer (22), | + | address unit (21), CPU read/write buffer (22), [i]Sprite Attribute Table[/i] (23), sprite |
shift register (24), and background shift register (25) are connected to terminals | shift register (24), and background shift register (25) are connected to terminals | ||
MD0 to MD15 through which data are transferred to and from the VRAM (7). | MD0 to MD15 through which data are transferred to and from the VRAM (7). | ||
− | The | + | The [i]Sprite Attribute Table buffer[/i] (23) is a memory for storing X and Y display |
positions, pattern codes and control data of sprites each composed of 16×16 dots as | positions, pattern codes and control data of sprites each composed of 16×16 dots as | ||
described in more detail later. | described in more detail later. | ||
Line 145: | Line 145: | ||
The sprite shift register (24) stores pattern and color data of a sprite read from a | The sprite shift register (24) stores pattern and color data of a sprite read from a | ||
sprite generator in the VRAM (7) which is accessed in accordance with the pattern | sprite generator in the VRAM (7) which is accessed in accordance with the pattern | ||
− | codes stored in the | + | codes stored in the [i]Sprite Attribute Table[/i] (23) as described in more detail later. |
The background shift register (25) stores pattern data, along with CG color, read | The background shift register (25) stores pattern data, along with CG color, read | ||
Line 153: | Line 153: | ||
The data bus buffer (26) is connected to terminals D0 to D15 through which data are | The data bus buffer (26) is connected to terminals D0 to D15 through which data are | ||
− | supplied and received. In the | + | supplied and received. In the [i]Video Display Controller[/i] 1, 8 or 16 bit interface is |
selected to comply with a data width of a system including the CPU (2) wherein the | selected to comply with a data width of a system including the CPU (2) wherein the | ||
terminals D0 to D7 among the terminals D0 to D15 are occupied when the 8 bit | terminals D0 to D7 among the terminals D0 to D15 are occupied when the 8 bit | ||
Line 166: | Line 166: | ||
The priority circuit (28) is connected to terminals VD0 to VD7 through which video | The priority circuit (28) is connected to terminals VD0 to VD7 through which video | ||
− | signals are supplied, and a | + | signals are supplied, and a [i]SP/BG[/i] (VD8) terminal being "H" when the video signals are |
of a sprite and being "L" when the video signals are of a background. | of a sprite and being "L" when the video signals are of a background. | ||
Line 173: | Line 173: | ||
thereinto, a RD terminal receiving a clock signal for the reading thereof, a WR | thereinto, a RD terminal receiving a clock signal for the reading thereof, a WR | ||
terminal receiving a clock signal for the writing thereof, and terminals A0 and A1 | terminal receiving a clock signal for the writing thereof, and terminals A0 and A1 | ||
− | which are connected to address bus of the CPU (2). Further, the | + | which are connected to address bus of the CPU (2). Further, the [i]Video Display[/i] |
− | Controller[/i] | + | [i]Controller[/i] (1) is provided with a [o]MRD[/o] terminal being "L" when the CPU (2) reads data |
from the VRAM (7), and a [o]MWR[/o] terminal being "L" when the CPU (2) writes data into the | from the VRAM (7), and a [o]MWR[/o] terminal being "L" when the CPU (2) writes data into the | ||
VRAM (7). | VRAM (7). | ||
</nowiki> | </nowiki> | ||
− | | [[Image:US4951038-fig2a.png | thumb | 500px | [Figure 2A] is a block diagram showing a | + | | [[Image:US4951038-fig2a.png | thumb | 500px | [Figure 2A] is a block diagram showing a [i]Video Display Controller[/i] for the control of writing video signals into VRAM and reading video signals therefrom.]] |
|- | |- | ||
| <nowiki> | | <nowiki> | ||
In [Figure 2B], there is shown an apparatus for displaying a sprite on a screen in an embodiment | In [Figure 2B], there is shown an apparatus for displaying a sprite on a screen in an embodiment | ||
according to the invention wherein the reference numerals 31 and 32 indicate a sprite | according to the invention wherein the reference numerals 31 and 32 indicate a sprite | ||
− | attribute table and sprite generator in the VRAM (7) respectively. The | + | attribute table and sprite generator in the VRAM (7) respectively. The [i]Sprite Attribute[/i] |
− | table[/i] | + | table[/i] (31) can include, for instance, sixty four sprites, while the sprite generator (32) |
− | can include, for instance one thousand and twenty-four sprites. In the | + | can include, for instance one thousand and twenty-four sprites. In the [i]Sprite Attribute[/i] |
− | + | [i]Table[/i] (31), addresses of 0 to 63 are assigned to the sixty-four sprites to give a | |
priority thereto in the order of the address 0>1>...>62>63. Each of the sprites in | priority thereto in the order of the address 0>1>...>62>63. Each of the sprites in | ||
composed of 16x16 bits, and includes X and Y coordinates, pattern codes and control | composed of 16x16 bits, and includes X and Y coordinates, pattern codes and control | ||
Line 194: | Line 194: | ||
signal are stored into a pattern code buffer (35) which can store a maximum of sixteen | signal are stored into a pattern code buffer (35) which can store a maximum of sixteen | ||
sprites by referring to a corresponding one of the addresses 0 to 63. A selector (36) | sprites by referring to a corresponding one of the addresses 0 to 63. A selector (36) | ||
− | selects a pattern code of the | + | selects a pattern code of the [i]Sprite Attribute Table[/i] (31) in accordance with an address |
stored in the pattern code buffer (35) to access the sprite generator (32) in regard to | stored in the pattern code buffer (35) to access the sprite generator (32) in regard to | ||
an address which is of a selected pattern code, thereby reading pattern data from the | an address which is of a selected pattern code, thereby reading pattern data from the | ||
sprite generator (32). The pattern data thus obtained are stored into a pattern data | sprite generator (32). The pattern data thus obtained are stored into a pattern data | ||
− | buffer (37) along with an X coordinate corresponding thereto read from the | + | buffer (37) along with an X coordinate corresponding thereto read from the [i]Sprite[/i] |
− | + | [i]Attribute Table[/i] (31). The storing of sprites into the pattern code buffer (35) is | |
− | performed at a | + | performed at a [i]Horizontal Display Period[/i] preceding to the present horizontal display |
period by one scanning raster, while the storing of the pattern data into the pattern | period by one scanning raster, while the storing of the pattern data into the pattern | ||
data buffer (37) is performed at a following horizontal retrace period. When a | data buffer (37) is performed at a following horizontal retrace period. When a | ||
Line 223: | Line 223: | ||
A register number "AR" is exclusive written into the address register designating one of | A register number "AR" is exclusive written into the address register designating one of | ||
the memory address write register to DMA VRAM-SATB source address register as shown in | the memory address write register to DMA VRAM-SATB source address register as shown in | ||
− | Figures 3C to 3U so that data are writing into the | + | Figures 3C to 3U so that data are writing into the [i]Video Display Controller[/i] (1) under the |
condition that the A1 and [o]CS[/o] terminals thereof are "L". | condition that the A1 and [o]CS[/o] terminals thereof are "L". | ||
Line 238: | Line 238: | ||
A bit corresponding to one of interruption jobs is set to be "H" in the status register | A bit corresponding to one of interruption jobs is set to be "H" in the status register | ||
to make the interruption active when a cause of the interruption which is enabled by an | to make the interruption active when a cause of the interruption which is enabled by an | ||
− | interruption permission bit of a | + | interruption permission bit of a [i]Control Register[/i] and [i]DMA Control Register[/i] as showing in |
Figures 3G and 3Q is occurred. When the status is read from the status register, the | Figures 3G and 3Q is occurred. When the status is read from the status register, the | ||
corresponding bit is cleared automatically. | corresponding bit is cleared automatically. | ||
Line 261: | Line 261: | ||
(4) bit 4 (DS) - finishing of DMA transfer | (4) bit 4 (DS) - finishing of DMA transfer | ||
− | It is indicated that data transfer between the VRAM and | + | It is indicated that data transfer between the VRAM and [i]Sprite Attribute Table[/i] |
buffer (23) is finished. | buffer (23) is finished. | ||
Line 310: | Line 310: | ||
| <nowiki> | | <nowiki> | ||
(g) Control Register (register number "05", [Figure 3G]) | (g) Control Register (register number "05", [Figure 3G]) | ||
− | An operating mode of the | + | An operating mode of the [i]Video Display Controller[/i] (1) is controlled in accordance with the |
− | following bits of the | + | following bits of the [i]Control Register[/i]. |
(1) bits 0 to 3 (IE) - enable of interruption request | (1) bits 0 to 3 (IE) - enable of interruption request | ||
Line 325: | Line 325: | ||
(3) bit 6 (SB) - sprite blanking | (3) bit 6 (SB) - sprite blanking | ||
It is decided whether a sprite should be displayed on a screen or not. | It is decided whether a sprite should be displayed on a screen or not. | ||
− | The control of the bit is effective in the following | + | The control of the bit is effective in the following [i]Horizontal Display Period[/i]. |
(3.1) "0" - blanking of a sprite | (3.1) "0" - blanking of a sprite | ||
(3.2) "1" - display of a sprite | (3.2) "1" - display of a sprite | ||
Line 331: | Line 331: | ||
(4) bit 7 (BB) - background blanking | (4) bit 7 (BB) - background blanking | ||
It is decided whether background should be displayed on a screen or not. | It is decided whether background should be displayed on a screen or not. | ||
− | The control of the bit is effective in the following | + | The control of the bit is effective in the following [i]Horizontal Display Period[/i]. |
(4.1) "0" - blanking of background | (4.1) "0" - blanking of background | ||
(4.2) "1" - display of background. | (4.2) "1" - display of background. | ||
Line 342: | Line 342: | ||
time. | time. | ||
− | In such occasions, the terminals VD0 and VD7 are all "L" while the | + | In such occasions, the terminals VD0 and VD7 are all "L" while the [i]SP/BG[/i] terminal is |
"H". On the other hand, when the bits 6 and 7 are both "1", there is released from | "H". On the other hand, when the bits 6 and 7 are both "1", there is released from | ||
the "burst mode". | the "burst mode". | ||
Line 449: | Line 449: | ||
(2) bits 8 to 11 (HDE) - horizontal display ending position | (2) bits 8 to 11 (HDE) - horizontal display ending position | ||
− | A period between an ending of a | + | A period between an ending of a [i]Horizontal Display Period[/i] and a rising edge of a |
horizontal synchronous signal is set as an unit of a character cycle. An optimum | horizontal synchronous signal is set as an unit of a character cycle. An optimum | ||
position of a horizontal display is set on a CRT display by the 7 bits. When it is | position of a horizontal display is set on a CRT display by the 7 bits. When it is | ||
Line 493: | Line 493: | ||
(q) DMA Control Register (register number "0F", [Figure 3Q]) | (q) DMA Control Register (register number "0F", [Figure 3Q]) | ||
(1) bit 0 (DSC) - enable an interruption at the finishing of transfer between the | (1) bit 0 (DSC) - enable an interruption at the finishing of transfer between the | ||
− | VRAM (7) and | + | VRAM (7) and [i]Sprite Attribute Table[/i] buffer (23) |
It is decided whether or not an interruption is enabled at the finishing time of | It is decided whether or not an interruption is enabled at the finishing time of | ||
the transfer. | the transfer. | ||
Line 520: | Line 520: | ||
Table buffer (23). | Table buffer (23). | ||
It is decided whether or not a repetition of a transfer between the VRAM (7) | It is decided whether or not a repetition of a transfer between the VRAM (7) | ||
− | and | + | and [i]Sprite Attribute Table[/i] buffer (23) is enabled. |
(5.1) "0"--disable | (5.1) "0"--disable | ||
(5.2) "1"--enabled | (5.2) "1"--enabled | ||
Line 554: | Line 554: | ||
(u) DMA VRAM-SATB Source Address Register (register number "13", [Figure 3U]) | (u) DMA VRAM-SATB Source Address Register (register number "13", [Figure 3U]) | ||
A starting address of a source address is allocated in a transfer between the VRAM (7) | A starting address of a source address is allocated in a transfer between the VRAM (7) | ||
− | and | + | and [i]Sprite Attribute Table[/i]d buffer (23). |
</nowiki> | </nowiki> | ||
| [[Image:US5319786-fig3u.png | thumb | 500px | [Figure 3U] DMA VRAM-SAT Source Address Register (DVSSR)]] | | [[Image:US5319786-fig3u.png | thumb | 500px | [Figure 3U] DMA VRAM-SAT Source Address Register (DVSSR)]] | ||
Line 587: | Line 587: | ||
|- | |- | ||
| <nowiki> | | <nowiki> | ||
− | In [Figures 6A/B], there are shown | + | In [Figures 6A/B], there are shown [i]Sprite Attribute Table[/i]d (SATs) (31) in the VRAM along with the |
− | sprite generator region (32). Each of the | + | sprite generator region (32). Each of the [i]Sprite Attribute Table[/i]s (31) is composed of |
16x4 bits, that is, four words to define a sprite. Therefore, sixty four sprites are | 16x4 bits, that is, four words to define a sprite. Therefore, sixty four sprites are | ||
− | defined by 256 words. In the | + | defined by 256 words. In the [i]Sprite Attribute Table[/i], lower 10 bits in the first word |
designate a horizontal position (0 to 1023) of a sprite. For this purpose, one of | designate a horizontal position (0 to 1023) of a sprite. For this purpose, one of | ||
0 to 1023 is written into a X coordinate therein. In the same manner, lower 10 bits | 0 to 1023 is written into a X coordinate therein. In the same manner, lower 10 bits | ||
Line 630: | Line 630: | ||
so that one sprite occupies 64 words. | so that one sprite occupies 64 words. | ||
− | The writing of data into a | + | The writing of data into a [i]Sprite Attribute Table[/i] (31) is performed such that the data |
are not transferred from the CPU (2) directly to the VRAM (7), but in DMA transfer from | are not transferred from the CPU (2) directly to the VRAM (7), but in DMA transfer from | ||
− | the CPU (2) to the | + | the CPU (2) to the [i]Sprite Attribute Table[/i] buffer (23). |
In operation, a sprite [i]SP[/i] having standard coordinates (2,2) is displayed on a display | In operation, a sprite [i]SP[/i] having standard coordinates (2,2) is displayed on a display | ||
screen (9) having 1024 display dots respectively in the X and Y directions as shown in | screen (9) having 1024 display dots respectively in the X and Y directions as shown in | ||
[Figure 7]. In displaying the sprite [i]SP[/i] thereon, the Y coordinates of the sixty-four | [Figure 7]. In displaying the sprite [i]SP[/i] thereon, the Y coordinates of the sixty-four | ||
− | + | [i]Sprite Attribute Table[/i]s (31) are compared in turn with a raster signal supplied from | |
the scanning raster signal producing circuit (33) at the coincidence detection | the scanning raster signal producing circuit (33) at the coincidence detection | ||
circuit (34) to pick up sprites each having a Y coordinate "2" which is then stored | circuit (34) to pick up sprites each having a Y coordinate "2" which is then stored | ||
in its stripe number among the stripe numbers 0 to 63 into the pattern code buffer (35) | in its stripe number among the stripe numbers 0 to 63 into the pattern code buffer (35) | ||
− | when a | + | when a [i]Horizontal Display Period[/i] of a scanning raster number "1" is started in the |
apparatus as shown in [Figure 2B]. In this occasion, sixteen of sprites can be stored | apparatus as shown in [Figure 2B]. In this occasion, sixteen of sprites can be stored | ||
in the pattern code buffer (35) at the maximum. During a horizontal retrace period | in the pattern code buffer (35) at the maximum. During a horizontal retrace period | ||
Line 647: | Line 647: | ||
raster number "2" is started, address signals are produced in the selector (36) in | raster number "2" is started, address signals are produced in the selector (36) in | ||
accordance with the sprite numbers stored in the pattern code buffer (35) and pattern | accordance with the sprite numbers stored in the pattern code buffer (35) and pattern | ||
− | codes in the | + | codes in the [i]Sprite Attribute Table[/i]s (31) so that pattern data are read from the |
sprite generator (32) in accordance with the address signals thus produced. The | sprite generator (32) in accordance with the address signals thus produced. The | ||
pattern data are stored in the pattern data buffer 37 along with X coordinates | pattern data are stored in the pattern data buffer 37 along with X coordinates | ||
− | corresponding thereto in the | + | corresponding thereto in the [i]Sprite Attribute Table[/i]s 31. When a horizontal display |
period of the scanning raster number "2" is started, the X coordinates stored in the | period of the scanning raster number "2" is started, the X coordinates stored in the | ||
pattern data buffer (37) are compared with counted values of the horizontal dot clock | pattern data buffer (37) are compared with counted values of the horizontal dot clock | ||
Line 665: | Line 665: | ||
moving the sprite [i]SP[/i] having the standard coordinates (2, 2) to a display position | moving the sprite [i]SP[/i] having the standard coordinates (2, 2) to a display position | ||
having a standard coordinates (X, Y) to be a sprite SP', the X and Y coordinates | having a standard coordinates (X, Y) to be a sprite SP', the X and Y coordinates | ||
− | (2, 2) of the | + | (2, 2) of the [i]Sprite Attribute Table[/i] 31 corresponding to the sprite [i]SP[/i] are only |
changed to be X and Y coordinates (x, y) without changing contents of the sprite | changed to be X and Y coordinates (x, y) without changing contents of the sprite | ||
generator 32 and necessitating the redefinition of a pattern. The sprites [i]SP[/i] and [i]SP[/i]' | generator 32 and necessitating the redefinition of a pattern. The sprites [i]SP[/i] and [i]SP[/i]' | ||
Line 676: | Line 676: | ||
example, 24 display patterns are obtained in accordance with the calculation | example, 24 display patterns are obtained in accordance with the calculation | ||
"4x3x2=24" so that a desired pattern can be selected from 24 patterns in accordance with | "4x3x2=24" so that a desired pattern can be selected from 24 patterns in accordance with | ||
− | control data in a | + | control data in a [i]Sprite Attribute Table[/i]. The four facets SG0 to SG3 are of different |
colors each to be designated by an area color code. | colors each to be designated by an area color code. | ||
Line 682: | Line 682: | ||
table (31) are explained. | table (31) are explained. | ||
</nowiki> | </nowiki> | ||
− | | [[Image:US5319786-fig6.png | thumb | 500px | [Figures 6A/6B] are explanatory diagrams showing a | + | | [[Image:US5319786-fig6.png | thumb | 500px | [Figures 6A/6B] are explanatory diagrams showing a [i]Sprite Attribute Table[/i] in the VRAM in the embodiment according to the invention.]] |
|- | |- | ||
| [[Image:US5319786-fig7.png | thumb | 500px | [Figure 7] is an explanatory diagram explaining a first operation in which a sprite is moved on a screen in the embodiment according to the invention.]] | | [[Image:US5319786-fig7.png | thumb | 500px | [Figure 7] is an explanatory diagram explaining a first operation in which a sprite is moved on a screen in the embodiment according to the invention.]] | ||
Line 701: | Line 701: | ||
|- | |- | ||
| <nowiki> | | <nowiki> | ||
− | In [Figure 11A], when a bit [o]X[/o] in a | + | In [Figure 11A], when a bit [o]X[/o] in a [i]Sprite Attribute Table[/i] (31) is set to be "1", a sprite |
is displayed to be reversed in a left-side right manner. On the other hand, when | is displayed to be reversed in a left-side right manner. On the other hand, when | ||
− | a bit [o]Y[/o] in the | + | a bit [o]Y[/o] in the [i]Sprite Attribute Table[/i] (31) is set to be "1", the sprite is displayed |
to be reversed in an upside down manner. As a matter of course, when the bits [o]X[/o] | to be reversed in an upside down manner. As a matter of course, when the bits [o]X[/o] | ||
and [o]Y[/o] are set to be "1", the sprite is displayed to be reversed in a left-size | and [o]Y[/o] are set to be "1", the sprite is displayed to be reversed in a left-size | ||
Line 727: | Line 727: | ||
In [Figures 12A/B/C], a CGY display mode as briefly explained before is again explained. In the | In [Figures 12A/B/C], a CGY display mode as briefly explained before is again explained. In the | ||
CGY display mode, two bits X[sub]3[/sub] and X[sub]2[/sub] of a pattern code in a | CGY display mode, two bits X[sub]3[/sub] and X[sub]2[/sub] of a pattern code in a | ||
− | + | [i]Sprite Attribute Table[/i] are controlled so as to be (0, 0), (0, 1), (1, 0) and (1, 1). | |
Therefore if it is "00001000110", an address map of a sprite generator is illustrated | Therefore if it is "00001000110", an address map of a sprite generator is illustrated | ||
as shown in [Figure 12A]. As a result, a sprite is displayed in 4CGY mode as shown | as shown in [Figure 12A]. As a result, a sprite is displayed in 4CGY mode as shown | ||
Line 793: | Line 793: | ||
1. An apparatus for displaying a sprite on the display screen comprising: | 1. An apparatus for displaying a sprite on the display screen comprising: | ||
− | + | [i]Sprite Attribute Table[/i]s each including coordinates indicating a display position of a | |
sprite, a pattern code defining said sprite in regard to pattern data, and control data | sprite, a pattern code defining said sprite in regard to pattern data, and control data | ||
defining a display mode of said sprite; | defining a display mode of said sprite; | ||
Line 830: | Line 830: | ||
said storing means stores said starting coordinates determined in accordance with | said storing means stores said starting coordinates determined in accordance with | ||
contents of a Horizontal Period Register, a Vertical Synchronism Register, and a | contents of a Horizontal Period Register, a Vertical Synchronism Register, and a | ||
− | + | [i]Vertical Display Register[/i]. | |
4. An apparatus for displaying a sprite on video display responsive to display scan | 4. An apparatus for displaying a sprite on video display responsive to display scan | ||
Line 836: | Line 836: | ||
counter, comprising: | counter, comprising: | ||
− | a memory for storing a | + | a memory for storing a [i]Sprite Attribute Table[/i], said table including coordinates |
indicating a display position of a sprite, a pattern code defining said sprite, and | indicating a display position of a sprite, a pattern code defining said sprite, and | ||
display control data defining a display mode of said sprite; | display control data defining a display mode of said sprite; |
Revision as of 15:09, 21 April 2014
Patent for Displaying Sprites
Note:
- Here is the Original Patent.
- This is a manually transposed version of the patent, please correct any errors you see.
- Terms of significance have been capitalized (to match it's abbreviation) and italicized.
- Many drawings have been replaced by more complete versions from Patent 5319786.
- Unintentionally missing information has been copied from Patent 5319786.
United States Patent Number: 4951038APPARATUS FOR DISPLAYING A SPRITE ON A SCREEN
Abstract
Apparatus for displaying a sprite on a screen comprises Sprite Attribute Tables each including coordinates indicating a display position of a sprite, a pattern code defining the sprite in regard to pattern data, and control data defining a display mode of the sprite. A sprite generator is address in accordance with the pattern code to supply the pattern data of a sprite to the pattern data buffer. The sprite is displayed in accordance with the coordinance thereof on the the screen. Therefore, the sprite is moved on the screen only by changing the coordinance of the corresponding Sprite Attribute Table.
4 Claims, 16 Drawing Sheets
Patent Text
APPARATUS FOR DISPLAYING A SPRITE ON A SCREEN
Field of the Invention
The invention related to an apparatus for displaying a sprite on a screen, and more particularly to an apparatus for displaying a sprite on a screen in which and image unit composed of a plurality of dots which is called a "sprite" is moved to be displayed on such a screen as a CRT display and so on.
Background of the Invention
One of the apparatuses for displaying an image unit composed of a plurality of dots on a CRT display is described in Japanese Patent Laid-open No. 11390/1982. In the apparatus for displaying am image unit on a CRT display, the image unit is moved on the CRT display in accordance with the subtraction between X value of standard coordinates and a horizontal standard line. In controlling signals for two adjacent horizontal scanning lines are alternately written into two line buffer memories so that image signals read from a character image memory are processed in accordance with the control signals thus read from the line buffer memories, thereby being displayed on the CRT display. The control signals comprise signals of the aforementioned subtractions in the X and Y directions so that the image unit is moved smoothly on the CRT display by increasing or decreasing the subtraction signal at an appropriate displaying time.
According to the apparatus for displaying an image unit on a CRT display, however, there is a disadvantage that a memory region is increased because the character image memory accessed after the control signals for the image unit are once written into the parallel line buffer memories.
There is a further disadvantage that enlarging the size of an image unit is difficult to be performed.
There is a still further disadvantage that, where the number of image units which designated to be displayed on a DRT display exceeds a predetermined number, an image unit exceeding the predetermined number is not displayed on the CRT display.
There is a yet still further disadvantage there there are provided additional registers into which the so-called "blanking mode" instruction is stored to perform the blanking mode wherein an image unit is moved from the edge of a CRT display to appear thereon or is moved to the edge therefor to disappear therefrom.
Summary of the Invention
Accordingly, it is an object of the invention to provide an apparatus for displaying a sprite on a screen in which a line buffer memories for storing control signals for a sprite are not necessary to be provided.
It is a further object of the invention to provide an apparatus for displaying a sprite on a screen in which the size of a sprite is easily controlled to be changed on a screen.
It is a still further object of the invention to provide an apparatus for displaying a sprite on a screen in which, where sprites more than a predetermined number to be displayed on a single horizontal scanning line are designated, the occurrence of such a designation is indicated.
It is a yet still further object of the invention to provide an apparatus for displaying a sprite on a screen in which the aforementioned blanking mode is easily performed.
According to the invention, an apparatus for displaying a sprite on a screen comprises, sprite attribute tabled each for including coordinates indicated a display position of a sprite, a pattern code defining said sprite in regard to pattern data, and control data defining a display mode of said sprite, first detection means for comparing a vertical position value of said coordinates of said sprite to be displayed with a dot clock signal to detect pattern data to be displayed, and means for controlling said screen to display said sprite to be displayed thereon in accordance with said pattern data to be displayed.
Description of Preferred Embodiments
Claims
Although the invention has been described to respect to specific embodiment for complete and clear disclosure the appended claims are not to thus limited but are to be constructed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within th basic teaching herein set forth. What is claimed is: 1. An apparatus for displaying a sprite on the display screen comprising: Sprite Attribute Tables each including coordinates indicating a display position of a sprite, a pattern code defining said sprite in regard to pattern data, and control data defining a display mode of said sprite; first detection means for comparing a vertical position value of said coordinates with a raster number to detect a sprite to be displayed; a sprite generator storing pattern data of said sprite; second detection means for comparing a horizontal position value of said coordinates of said sprite to be displayed with a dot clock signal to detect pattern data to be displayed; a pattern data buffer for storing pattern data of said sprite to be displayed in accordance with the reading thereof from said sprite generator; means for storing standard coordinates of a display region on said screen; a gate circuit for providing said pattern data stored in said pattern data buffer to said screen; ands means for controlling said screen to display said sprite to be displayed thereon in accordance with said pattern data to be displayed, wherein said controlling means decides selectively an allowance of an inhibition of said transmission of said pattern data in accordance with a comparison of said coordinates indicating said display position with said standard coordinates. 2. An apparatus for displaying a sprite on a display screen according to claim wherein: said storing means stored starting coordinates of said display region; and said controlling means inhibits said transmission of said pattern data when said coordinates indicate said display position is less than said starting coordinates. 3. An apparatus for displaying a sprite on a display screen according to claim 2, wherein: said storing means stores said starting coordinates determined in accordance with contents of a Horizontal Period Register, a Vertical Synchronism Register, and a Vertical Display Register. 4. An apparatus for displaying a sprite on video display responsive to display scan information supplied by a Vertical Scanning Raster Register and a Horizontal Dot Clock counter, comprising: a memory for storing a Sprite Attribute Table, said table including coordinates indicating a display position of a sprite, a pattern code defining said sprite, and display control data defining a display mode of said sprite; a first coincidence detector for comparing a vertical position value of said coordinates store in said memory with a raster number supplied by the vertical scanning register to detect a sprite to be displayed; a sprite generator storing pattern data of said sprite to be displayed; a pattern data buffer for storing pattern data from said sprite generator of said sprite to be displayed; a second coincidence detector for comparing a horizontal position value of said coordinates of said sprite to be displayed from said memory with a dot clock signal supplied by the horizontal dot clock counter and, in response, supplying a portion of said pattern data to be displayed received from said pattern data buffer; a start coordinates registration circuit for storing boundary coordinates defining a display region; a controller receiving said boundary coordinates from said start coordinates registration circuit and, in response to detecting a display position within said boundary coordinates, generating a display control signal; and a gate circuit for receiving said portion of said pattern data from said pattern data data and, in response to said display display control signal from said controller, providing said portion of said pattern data to said video display.