View source for Patent 5030946

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== Patent for VRAM access via VDC/CPU ==
{{:Patent Style}}</onlyinclude>Note: all mentions of "dot" have been replaced with "pixel"[br]<onlyinclude>
Note: terminals with a [i]High[/i] value are a binary [i]1[/i] and [i]Low[/i] is a binary [i]0[/i].

[[Patent 5030946 | Full Patent]]

[http://www.google.com/patents/US5030946 Original Patent]

[pre]
United States Patent Number: [b]5030946[/b]

[b]APPARATUS FOR THE CONTROL OF AN ACCESS TO A VIDEO MEMORY[/b]

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=== Abstract ===
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An apparatus for the control of an access to a video memory comprises a memory width register having a content of a number of pixel periods by which an access timing is determined to address a video memory. Therefore, an access timing is easily controlled dependent on a memory speed of the video memory only by changing the content of the memory width register. When the video memory is accessed during a display cycle of the video memory, video data may be stored in a buffer memory, and transferred from the buffer memory after the display cycle is finished.
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=== Field of the Invention ===

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The invention relates to an apparatus for the control of an access to a video memory, and more particularly to an apparatus for the control of an access to a video memory in which a number of pixel periods is controlled at the time of an access to a video memory and/or a timing of a data transfer is controlled during a display cycle of a video memory.
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=== Background of the Invention ===

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There has been used an apparatus for the control of an access to a video memory in which an access is allocated from a CPU to a video memory during the first half of 4 bits in a horizontal one character cycle of 8 bits, and an access is allocated to a character generator of the video memory during the latter half of 4 bits therein. In the apparatus for the control of an access to a video memory, flickers are prevented from being occurred on a screen because the writing and reading of data which are performed from the CPU to the video memory and the access to the character generator of the video memory are divided sequentially.

According to the apparatus for the control of an access to a video memory, however, there is a disadvantage that an access of the video memory can not be controlled in its timing because the access timing is fixed as mentioned before. In a personal computer in which a processing time is widely varied, for instance, from 40 ns to 139 ns dependent on a resolution of the screen, therefore, a property of the video memory is not sufficiently utilized even if the video memory is a high speed memory. On the other hand, a low speed memory can not be used in an apparatus in which a high speed memory is not required in view of a specified characteristic in a case where an access timing is fixed in a high speed mode.

There is a further disadvantage that a throughput of the CPU is decreased because the CPU has to wait the writing of data into the video memory and reading of data therefrom during a display cycle of the video memory, although flickers are prevented from being occurred on the screen.
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=== Summary of the Invention ===

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Accordingly, it is an object of the invention to provide an apparatus for the control of an access to a video memory in which an access to a video memory can be easily controlled in its timing dependent on a speed of a video memory.

It is another object of the invention to provide an apparatus for the control of an access to a video memory in which a throughput of a CPU is improved.

According to the invention, an apparatus for the control of an access to a video memory comprises:
*register means storing a number of pixel signals for the access to a video memory
*means for deciding said number of pixel periods in accordance with said content of said register means
*means for addressing said video memory at timings determined in accordance with said number of pixel periods
*means for latching video data which are read from said video memory at said timings
wherein a pattern defined by said video data is displayed on a screen.

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=== Description of Preferred Embodiments ===
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In [Figure 1], there is shown an apparatus for displaying an image on a screen which is mainly composed of a [i]Video Display Controller[/i] (1), a [i]CPU[/i] (2), a [i]Video Color Encoder[/i] (3), and a [i]Programmable Sound Generator[/i] (4). The [i]Video Display Controller[/i] (1) supplies the [i]Video Color Encoder[/i] (3) with image data for a story which are read from a [i]VRAM[/i] (7) under the control of the [i]CPU[/i] (2) reading a program stored in a [i]ROM[/i] (5). The [i]CPU[/i] (2) controls a [i]RAM[/i] (6) to store data, calculation or arithmetical results etc. temporarily in accordance with a program stored in the [i]ROM[/i] (5). The [i]Video Color Encoder[/i] (3) is supplied with image data to produce RGB analog signals or video color signals including luminance signals and color difference signals to which the RGB signals are matrix-converted by using color data stored therein. The programmable sound generator 4 is controlled by the [i]CPU[/i] (2) reading a program stored in the [i]ROM[/i] (5) to produce audio signals making left and right stereo sounds. The video color signals produced at the [i]Video Color Encoder[/i] (3) are of composite signals supplied through an [i]interface[/i] (8) to a [i]video display[/i] (9), while the RGB analog signals are directly supplied to a [i]video display[/i] (9) which is used as an exclusive monitor apparatus. The left and right analog signals supplied from the [i]Programmable Sound Generator[/i] (4) are amplified at amplifiers 11a and 11b to make sounds at speakers 12a and 12b.
| [[Image:US4951038-fig1.png | thumb | 500px | [Figure 1] is a block diagram showing an apparatus for displaying an image on a screen in which an apparatus for the control of an access to a video memory according to the invention is included.]]
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In [Figure 2A], there is shown the [i]Video Display Controller[/i] (1) transferring data between the [i]CPU[/i] (2) and [i]VRAM[/i] (7) which comprises a [i]control unit[/i] (20) including various kinds of registers to be described later, an [i]address unit[/i] (21), a [i]CPU read/write buffer[/i] (22), and [i]sprite shift register[/i] (24), a [i]background shift register[/i] (25), a [i]data bus buffer[/i] (26), a [i]synchronic circuit[/i] (27), and a [i]priority circuit[/i] (28).

The [i]control unit[/i] (20) is provided with a [o]BUSY[/o] terminal being [i]Low[/i] to keep the [i]CPU[/i] (2) writing data into the [i]VRAM[/i] (7) or reading data therefrom in a case where the [i]Video Display Controller[/i] (1) is not in time for the writing or reading of the date, an [o]IRQ[/o] terminal supplying an interruption request signal, a CK terminal receiving a clock signal of a frequency for one pixel periods (one picture element), a [o]RESET[/o] terminal receiving a reset signal for initializing the [i]Video Display Controller[/i] (1), and an EX 8/[o]16[/o] terminal receiving a data bus width signal for selecting one of 8 and 16 bit data buses.

The [i]address unit[/i] (21) is connected to terminals MAO to MA15 supplying address signals for the [i]VRAM[/i] (7) which has, for instance, a special address region of 65,536 words. The [i]address unit[/i] (21), [i]CPU read/write buffer[/i] (22), [i]Sprite Attribute Table[/i] (23), [i]sprite shift register[/i] (24), and [i]background shift register[/i] (25) are connected to terminals MD 0 to MD 15 through which data are transferred to and from the [i]VRAM[/i] (7).

The [i]Sprite Attribute Table buffer[/i] (23) is a memory for storing X and Y display positions, pattern codes and control data of sprites each composed of 16×16 pixels as described in more detail later.

The [i]sprite shift register[/i] (24) stores pattern and color data of a sprite read from a sprite generator in the [i]VRAM[/i] (7) which is accessed in accordance with the pattern codes stored in the [i]Sprite Attribute Table[/i] (23) as described in more detail later.

The [i]background shift register[/i] (25) stores pattern data, along with CG color, read from a character generator in the [i]VRAM[/i] (7) in accordance with an address based on a character code of a background attribute table in the [i]VRAM[/i] (7) which is accessed in an address decided by a raster position as also described in more detail later.

The [i]data bus buffer[/i] (26) is connected to terminals D0 to D15 through which data are supplied and received. In the [i]Video Display Controller[/i] (1), 8 or 16 bit interface is selected to comply with a data width of a system including the CPU2 wherein the terminals D0 to D7 among the terminals D0 to D15 are occupied when the 8 bit interface is selected.

The [i]synchronic circuit[/i] (27) is connected to a DISP terminal indicating a display period, a [o]VSYNC[/o] terminal from which a vertical synchronous signal for a [i]video display[/i] (9) is supplied and in which an external vertical synchronous signal is received, and a [o]HSYNC[/o] terminal from which a horizontal synchronous signal for a [i]video display[/i] (9) is supplied and in which an external horizontal synchronous signal is received.

The [i]priority circuit[/i] (28) is connected to terminals VD0 to VD7 through which video signals are supplied, and a [i]SP/BG[/i] (VD8) terminal being [i]High[/i] when the video signals are of a sprite and being [i]Low[/i] when the video signals are of a background.

The aforementioned [i]control unit[/i] (20) is also connected to a [o]CS[/o] terminal being [i]Low[/i] wherein the [i]CPU[/i] (2) is able to read data from registers therein and sprite data thereinto, a [o]RD[/o] terminal receiving a clock signal for the reading thereof, a [o]WR[/o] terminal receiving a clock signal for the writing thereof, and terminals A0 and A1 which are connected to address bus of the [i]CPU[/i] (2). Further, the [i]Video Display Controller[/i] (1) is provided with a [o]MRD[/o] terminal being [i]Low[/i] when the [i]CPU[/i] (2) reads data from the [i]VRAM[/i] (7), and a [o]MWR[/o] terminal being [i]Low[/i] when the [i]CPU[/i] (2) writes data into the [i]VRAM[/i] (7).
| [[Image:US4951038-fig2a.png | thumb | 500px | [Figure 2] is a block diagram showing a video display controller for the control of writing video signals into a VRAM and reading video signals therefrom.]]
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In [Figure 2B], there is shown an apparatus for displaying a sprite on a screen which is included in the apparatus of [Figure 1] wherein the reference numerals 31 and 32 indicate a sprite attribute table and sprite generator in the [i]VRAM[/i] (7) respectively. The [i]Sprite Attribute Table[/i] (31) can include, for instance, sixty-four sprites, while the [i]Sprite Generator[/i] (32) can include, for instance, one thousand and twenty-four sprites. In the [i]Sprite Attribute Table[/i] (31), addresses of 0 to 63 are assigned to the sixty-four sprites to give a priority thereto in the order of the address 0>1>. . . >62>63. Each of the sprites is composed of 16×16 bits, and includes X and Y coordinates, pattern codes and control data. As to each of the sprites, the Y coordinate is compared with a raster signal supplied from a scanning raster producing circuit 33 in a [i]coincidence detection circuit[/i] (34) whereby sprites each having a Y coordinate coincident with a raster signal are stored into a [i]pattern code buffer[/i] (35) which can store a maximum number of 16 sprites by referring to a corresponding one of the addresses 0 to 63. A [i]selector[/i] (36) selects a pattern code of the [i]Sprite Attribute Table[/i] (31) in accordance with an address stored in the [i]pattern code buffer[/i] (35) to access the [i]Sprite Generator[/i] (32) in regard to an address which is of a selected pattern code, thereby reading pattern data from the [i]Sprite Generator[/i] (32). The pattern data thus obtained are stored into a [i]pattern data buffer[/i] (37) along with an X coordinate corresponding thereto read from the [i]Sprite Attribute Table[/i] (31). The storing of sprites into the [i]pattern code buffer[/i] (35) is performed at a horizontal display period preceding to the present horizontal display period by one scanning raster, while the storing of pattern data into the [i]pattern data buffer[/i] (37) is performed at a following horizontal retrace period. When a scanning raster at which pattern data are displayed has come, the X coordinate thus stored in the [i]pattern data buffer[/i] (37) is compared with a counted value of a horizontal pixel period clock counter 38 in a [i]coincidence detection circuit[/i] (39) whereby pattern data having an X coordinate coincident with the counted value are supplied to a [i]parallel/serial converting circuit[/i] (40). In the [i]parallel/serial converting circuit[/i] (40), parallel pattern data are converted into serial pattern data which are supplied through a [i]gate circuit[/i] (42) to a [i]video display[/i] (9). The [i]gate circuit[/i] (42) is controlled to be turned on and off in accordance with a content of a [i]starting coordinates registration circuit[/i] (43) by the [i]CPU[/i] (2). The content thereof is X and Y coordinates by which the starting coordinates of a display region is defined on a display screen.
| [[Image:US4951038-fig2b.png | thumb | 500px | [Figure 2] is a block diagram showing an apparatus for displaying a sprite on a screen in the apparatus of [Figure 1].]]
{{:Patent VDC Registers}}
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In [Figure 4A, there is shown an address in a background attribute table for a character on a fictitious screen. A character and color to be displayed at each character position are stored in the background attribute table. A predetermined number of background attribute tables are stored in a region the first address of which is [i]0[/i] in the [i]VRAM[/i] (7). The fictitious screen shown therein which is one example is of 32×32 characters (1F=32).
| [[Image:US4951038-fig4a.png | thumb | 500px | [Figure 4A] is an explanatory diagram showing a fictitious screen in the apparatus of [Figure 1].]]
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In [Figure 4B, there is shown a screen which is framed by writing respective predetermined values into the aforementioned horizontal synchronous register, horizontal display register, vertical synchronous register and vertical display register as shown in [Figures 3L, 3M, 3N and 3O]. Although the respective predetermined values for the registers are not explained here, a display region is defined in accordance with "HDW+1" in the horizontal display register and "VDW+1" in the vertical display register. In the embodiment, the starting coordinates (x,y) for the display region is indicated to be as (32, 64).
| [[Image:US4951038-fig4b.png | thumb | 500px | [Figure 4B] is an explanatory diagram showing a display region on a screen in the apparatus of [Figure 1].]]
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In [Figures 5A and 5B], there are shown background attribute tables (BATs) in the [i]VRAM[/i] (7) each of 16 bits to have a character code of lower 12 bits for designating a pattern number of a character and a CG color of upper 4 bits for designating a CG color code.
| [[Image:US4951038-fig5.png | thumb | 500px | [Figure 5A and 5B] are explanatory diagrams showing a background attribute table in the VRAM in the apparatus of [Figure 1].]]
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[Figures 6A and 6B]
| [[Image:US4951038-fig6.png | thumb | 500px | [Figures 6A and 6B] are explanatory diagrams showing a sprite attribute table in the VRAM in the apparatus of [Figure 1].]]
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[Figure 7]
| [[Image:US4951038-fig7.png | thumb | 500px | [Figure 7] is an explanatory diagram explaining an operation in which a sprite is moved on a screen in the apparatus of [Figure 1].]]
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[Figure 8]
| [[Image:US4951038-fig8&9.png | thumb | 500px | [Figure 8] is an explanatory diagram explaining an operation in which a plurality of facets are combined to provide a sprite in the apparatus of [Figure 1].]]
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[Figure 10]
| [[Image:US4951038-fig10.png | thumb | 500px | [Figure 10A to 10E] are explanatory diagrams showing an operation in which a size of a sprite is enlarged in the apparatus of [Figure 1].]]
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In [Figure 11A] , there is shown an apparatus for the control of an access to a video memory in an embodiment according to the invention. The apparatus for the control of an access to a video memory comprises an [i]oscillator[/i] (51) for producing oscillation signals, a [i]frequency divider[/i] (52) for dividing a frequency of the oscillation signals by a predetermined dividing ratio to produce pixel clock signals, a [i]memory width register[/i] (3K) as already explained in [Figure 3K] having a content of a number of pixel periods dependent on a memory speed of the [i]VRAM[/i] (7), a number of [i]pixel periods decision circuit[/i] (53) for deciding a pixel width in accordance with the content of the [i]memory width register[/i] (3K), means (54, 55 and 56) for producing a CPU address signal, DMA address signal and CG address signal respectively to designate addresses in an access to the [i]VRAM[/i] (7), an [i]address selector[/i] (57) for selecting an address at an access timing which is set by the number of [i]pixel periods decision circuit[/i] (53), and a data [i]latch circuit[/i] (58) for latching data read from the [i]VRAM[/i] (7). The [i]VRAM[/i] (7) is shown in [Figure 11A] to include a [i]VRAM region[/i] (33) of a fictitious screen as described in [Figure 4A] and a [i]Character Generator[/i] (34) which is also shown in [Figure 11B]. One character of the [i]Character Generator[/i] (34) is composed of four facets CH0 Ch1, CH2 and CH3 each having 8×8 pixels by which a pattern is defined by 16 words of 8 words for the facets CH0 and CH1 and other 8 words for the facets CH2 and CH3. The characters are addressed by the first addresses of the facets CHOs shown by A0, A1, A2 . . . which are defined by character codes of background attribute tables as described in [Figures 5A and 5B].

In operation, when a horizontal display of the scanning raster number [i]0[/i] is started, the VM bits of the [i]memory width register[/i] (3K) are checked by the number of [i]pixel periods decision circuit[/i] (53). If it is assumed that a content of the VM bits is [i]00[/i], a number of pixel periods of an access to the [i]VRAM[/i] (7) is decided to be [i]1[/i] as defined in the table on page 19. Accordingly, the [i]VRAM[/i] (7) is accessed in accordance with a CPU address signal from the [i]CPU address signal means[/i] (54) under the control of the [i]address selector[/i] (57) at the first pixel timing among 8 pixels of one character cycle. Next, the [i]VRAM region[/i] (33) of the [i]VRAM[/i] (7) is accessed at an address [i]0[/i] in accordance with a CG address signal from the [i]CG address signal means[/i] (56) at the second pixel timing. At this moment, a character code and a CG color are read from a background attribute table, as shown in [Figures 5A and 5B], of the address [i]0[/i]. Thereafter, accesses are performed from the [i]CPU[/i] (2 in [Figure 1]) to the [i]VRAM[/i] (7) at the third and fifth pixel timings except for the fourth pixel timing, and the [i]Character Generator[/i] (34) is accessed at the sixth pixel timing. In the access to the [i]Character Generator[/i] (34), a CG address signal of the [i]CG address signal means[/i] (56) is determined in accordance with a pattern number corresponding to a character code which is previously checked whereby display data are read from the facets CH0 and CH1 thereof. After the seventh pixel timing, display data are further read from the facets CH2 and CH3 in accordance with the same address signal at the 8 pixel timing. As a result, one character is formed in accordance with the display data of the four facets CH0 to CH3 which are latched in the data [i]latch circuit[/i] (58). A display of the address [i]0[/i] is performed on the [i]video display[/i] (9 in [Figure 1]) in accordance with the data thus latched in the data [i]latch circuit[/i] (58) wherein a color of the display is determined by the CG color in the background attribute table. In the horizontal displays which follow the horizontal display of the scanning raster line [i]0[/i], the same operation as explained above will be repeated.

On the other hand, if it is assumed that a content of the VM bits is [i]01[/i], [i]10[/i] or [i]11[/i], the [i]VRAM[/i] (7) is accessed with a number of pixel periods is [i]2[/i], [i]2[/i] or [i]4[/i]. For this reason, a content of the VM bits is determined dependent on a memory speed of the [i]VRAM[/i] (7).

In another operation, it is assumed that a content of the VM bits is [i]00[/i] in the [i]memory width register[/i] (3K) to provide a number of pixel periods of one pixel, and that a content of the IW bits is [i]00[/i] in the control register as shown in [Figure 3G] to provide an address increment width [i]1[/i]. An operation in which data are written into the [i]VRAM[/i] (7) is started after the first address for writing the data is written into the memory address write register as shown in [Figure 3C]. When the [i]VRAM[/i] (7) is accessed from the [i]CPU[/i] (2) as shown in [Figure 12] by the indication [i]CPU→VRAM[/i], the data are held in the [i]CPU read/write buffer[/i] (22 in [Figure 2A]), if the writing of the data is collided in regard to its timing with a display cycle of the [i]VRAM[/i] (7). For this reason, the [i]CPU[/i] (2) is released from the writing of the data as changed from [i]0[/i] to [i]1[/i] in regard to a timing chart of [i]CPU→VRAM[/i]. Thereafter, when the display cycle of the [i]VRAM[/i] (7) is finished, the data thus held in the [i]CPU read/write buffer[/i] (22) are written, as shown by the indication [i]VRAM [o]WR[/o][/i], into the [i]VRAM[/i] (7) at the address which is designated by the memory address write register of [Figure 3C]. At this moment, a content of the memory address write register is incremented by one. On the other hand, in a case where the [i]VRAM[/i] (7) is accessed from the [i]CPU[/i] (2) when data are held in the [i]CPU read/write buffer[/i] (22), the condition [i][o]WAIT[/o][/i] becomes effective in the [i]CPU[/i] (2) so that a wait signal is produced at the [o]BUSY[/o] terminal connected to the [i]control unit[/i] (20 in [Figure 2A]). Therefore, the condition [i][o]WAIT[/o][/i] is much decreased in the number of occurrences in accordance with the provision of the [i]CPU read/write buffer[/i] (22).

In the same manner as described above, the [i]VRAM[/i] (7) is accessed from the [i]CPU[/i] (2) so that data are read from the VRAM as shown in [Figure 12] by the indication [i]CPU ← VRAM[/i]. Data which are read from the [i]VRAM[/i] (7) at an address designated by the memory address read register as shown in [Figure 3D] are once held in the [i]CPU read/write buffer[/i] (22), when the access to the [i]VRAM[/i] (7) is collided with the display cycle of the [i]VRAM[/i] (7). When the display cycle of the [i]VRAM[/i] (7) is finished, the data thus held in the [i]CPU read/write buffer[/i] (22) are transferred to the [i]CPU[/i] (2) as shown by the indication [i]VRAM [o]RD[/o][/i]. At this moment, a content of the memory address read register is incremented by one.

Otherwise, if the [i]CPU read/write buffer[/i] (22) is not provided, the condition [i][o]WAIT[/o][/i] is increased in the number of occurrences as shown in [Figure 13] so that a throughput of the [i]CPU[/i] (2) is decreased. In more detail, the condition [i][o]WAIT[/o][/i] is continued in the [i]CPU[/i] (2) until the display cycle of the [i]VRAM[/i] (7) is finished, when the [i]VRAM[/i] (7) is accessed from the [i]CPU[/i] (2) for the writing of data ([i]CPU→VRAM[/i]) and the reading thereof ([i]CPU ← VRAM[/i]) during that cycle. When the display cycle of the [i]VRAM[/i] (7) is finished, data are written into the [i]VRAM[/i] (7) as shown by the indication [i]VRAM [o]WR[/o][/i], and read from the VRAM as shown by the indication [i]VRAM [o]RD[/o][/i] whereby flickers are prevented from being occurred on a screen.
| [[Image:US5030946-fig11a.png | thumb | 500px | [Figure 11A] is a block diagram showing an apparatus for the control of an access to a video memory in an embodiment according to the invention.]]
[[Image:US5030946-fig11b.png | thumb | 200px | [Figure 11B] is an explanatory diagram showing a character generator in the apparatus of [Figure 11A].]]
[[Image:US5030946-fig12.png | thumb | 500px | [Figure 12 and 13] are timing charts showing operations in the apparatus of [Figure 11A and a conventional apparatus for the control of an access to a video memory respectively.]]
[[Image:US5030946-fig13.png | thumb | 500px | [Figure 12 and 13] are timing charts showing operations in the apparatus of [Figure 11A and a conventional apparatus for the control of an access to a video memory respectively.]]
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=== Claims ===

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Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to thus limited but are to be construed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.

What is claimed is:
<nowiki>
[ol]
[li] An apparatus for the control of an access to a video memory comprising:
  [ul]
    [li] register means for storing a number of pixel periods within a character cycle for processing the video memory.
    [li] means for deciding said number of pixel periods in accordance with said content of said register means.
    [li] means for addressing said video memory at timings determined in accordance with said number of pixel periods.
    [li] means for latching video data read from said video memory at said timings.
  [/ul]
    wherein a pattern defined by said video data is displayed on a display screen.
[li] An apparatus for the control of an access to a video memory according to claim 1.[br]
    wherein said video data are read from a character generator in said video memory, and said character generator is addressed in accordance with a character code stored in a background attribute table included in said video memory.
[li] An apparatus for the control of an access to a video memory according to claim 2.[br]
    wherein said character generator includes four facts which are combined to define said pattern.
[li] An apparatus for the control of an access to a video memory according to claim 2.[br]
    further comprising buffer means for storing said video data which are read from said video memory during a display cycle of said video memory, said video data being stored until said display cycle of said video memory is finished.
[li] An apparatus for the control of an access to a video memory according to claim 1, wherein said means for deciding said number of pixel periods includes means for generating a frequency having a period equal to said pixel period.
[li] An apparatus for the control of an access to a video memory according to claim 5 wherein said means for generating a frequency having a period equal to said pixel period includes an oscillator circuit and a frequency divider.
[li] An apparatus for the control of an access to a video memory according to claim 1, wherein said means for addressing said video memory includes:
  [ul]
    [li] a plurality of address registers.
    [li] address selector means responsive to said means for deciding said number of pixel periods for selecting one of said address registers to be a selected address register and addressing said video memory in response to a content of said selected address register.
  [/ul]
[li] An apparatus for the control of an access to a video memory according to claim 7, wherein said means for deciding said number of pixel periods includes means for generating a frequency having a period equal to said pixel period.
[li] An apparatus for the control of an access to a video memory according to claim 8, wherein said means for generating a frequency having a period equal to said pixel period includes an oscillator circuit and a frequency divider.
[li] An apparatus for the control of an access to a video memory comprising:
  [ul]
    [li] a video memory for storing video data
    [li] means for addressing said video memory
    [li] buffer means for storing video data to be written into said video memory and to be read out from said video memory
    [li] means for controlling said buffer means to store said video data, and producing a wait signal to suspend an accessing of said addressing means to said video memory,
  [/ul]
    wherein said controlling means controls said buffer means to store said video data without producing said wait signal, when said video memory is addressed for a display cycle of said video memory,
  [ul]
    [li] said controlling means controls said addressing means to access said video memory to transfer said video data stored in said buffer means when said display cycle is finished, and
    [li] said controlling means generates said wait signal when said video memory is to be accessed by said addressing means during a period when said video data is stored in said buffer means.
  [/ul]
[li] An apparatus for the control of an access to a video memory according to claim 10, wherein said video memory includes timing means for generating a frequency having a period equal to said pixel period.
[li] An apparatus for the control of an access to a video memory according to claim 11, wherein said timing means includes an oscillator circuit and a frequency divider.
[li] An apparatus for the control of an access to a video memory according to claim 10, wherein said means for addressing said video memory includes:
  [ul]
    [li] a plurality of address registers.
    [li] address selector means responsive to a timing signal having a frequency with a period equal to a pixel period for selecting one of said address registers to be a selected address register and addressing said video memory in response to a content of said selected address register.
  [/ul]
[li] An apparatus for the control of an access to a video memory according to claim 13, wherein said video memory includes timing means for generating said timing signal.
[li] An apparatus for the control of an access to a video memory according to claim 14, wherein said timing means includes an oscillator circuit and a frequency divider.
[/ol]
</nowiki>
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[[Category:Patents]]